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Physical Design/PDK methodology Engineer

Hello Dear Readers, At Applied Materials Bangalore, there is a vacancy for a Physical Design/PDK methodology Engineer role. Applied Materials is a global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service cutting-edge equipment that helps our customers manufacture display and semiconductor chips – the brains of devices we use every day. As the foundation of the global electronics industry, Applied enables the exciting technologies that literally connect our world – like AI and IoT. If you want to push the boundaries of materials science and engineering to create next generation technology, join us to deliver material innovation that changes the world.  Key Responsibility: Expertise in PDK enablement and library  validation/automation. Hands-on experience with LVS/Parasitic extraction/standard cell characterization flows and methodologies Design/System level experience with DTCO and ...
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Physical Design Engineer PEX at Sintegra Inc.

 Hello Dear Readers, 

Currently at Sintegra Inc. vacancy for Physical Design Engineer PEX role.

As a Parasitic Extraction Engineer at Sintegra, you will be responsible for developing, maintaining, and qualifying our sign-off extraction flows and methodologies. You will work with industry-standard extraction tools, ensuring the accuracy and efficiency of our IC designs through meticulous parasitic extraction and correlation processes.

Key Responsibilities:

  • Develop, maintain, and qualify sign-off extraction flows and methodologies to ensure accurate parasitic extraction.
  • Utilize industry-standard extraction tools such as Synopsys StarRC and Cadence Quantus QRC to perform detailed parasitic extraction.
  • Perform SPEF (Standard Parasitic Exchange Format) correlation and hierarchical extraction to validate extraction accuracy and optimize extraction flows.
  • Collaborate with design teams to integrate extraction methodologies into the overall IC design flow.
  • Write and maintain scripts in Tcl and Python to automate extraction processes and improve workflow efficiency.
  • Conduct thorough analysis and troubleshooting of extraction-related issues to ensure high-quality design outputs.
  • Stay updated with the latest industry trends and advancements in extraction tools and methodologies.

Qualifications:

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
  • Strong/Solid Background in the CAD Semiconductor area.
  • Deep experience with industry-standard extraction tools such as Synopsys StarRC and Cadence Quantus QRC.
  • Proven experience with SPEF correlation and hierarchical extraction flows/methodologies.
  • Proficiency in scripting languages such as Tcl and Python.
  • Knowledge of IC design, physical design, and electronic design automation (EDA) tools.

Preferred Qualifications:

  •  Experience in post-layout simulation and analysis.
  • Familiarity with timing analysis and signal integrity analysis.



Comments

  1. Anonymous8 June 2024 at 06:33

    Applied and got a call also thanks for sharing

    ReplyDelete
  2. Anonymous9 June 2024 at 21:03

    I cannot apply though LinkedIn bcoz whenever i try to apply through " easy apply" option in LinkedIn it shows some error

    ReplyDelete

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