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RTL Design Engineer at Skyroot Aerospace

Hello, Dear Readers, Skyroot Aerospace has a vacancy for the RTL Design Engineer role. About Skyroot Aerospace: A cutting-edge startup founded by ex-ISRO scientists. Dedicated to affordable space access, we're rewriting aerospace technology rules. Our dynamic team fosters inventiveness, collaboration, and relentless excellence. Join us on a transformative journey to redefine space possibilities. Welcome to the forefront of space innovation with Skyroot Aerospace! Purpose of role: Understand architectural requirements and Design micro-architecture, implement design blocks using VHDL/Verilog for FPGA based Avionics packages for orbital launch vehicles and ground infrastructure. Job Requirements: 2+ Years of RTL and system design experience. Strong knowledge on Digital System Design (DSD). Strong knowledge of RTL/SoC design/integration with VHDL/Verilog. Strong knowledge in problem solving and debugging skills. Ability to understand architectural requirements and Design micro-archite...
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Physical Design Engineer PEX at Sintegra Inc.

 Hello Dear Readers, 

Currently at Sintegra Inc. vacancy for Physical Design Engineer PEX role.

As a Parasitic Extraction Engineer at Sintegra, you will be responsible for developing, maintaining, and qualifying our sign-off extraction flows and methodologies. You will work with industry-standard extraction tools, ensuring the accuracy and efficiency of our IC designs through meticulous parasitic extraction and correlation processes.

Key Responsibilities:

  • Develop, maintain, and qualify sign-off extraction flows and methodologies to ensure accurate parasitic extraction.
  • Utilize industry-standard extraction tools such as Synopsys StarRC and Cadence Quantus QRC to perform detailed parasitic extraction.
  • Perform SPEF (Standard Parasitic Exchange Format) correlation and hierarchical extraction to validate extraction accuracy and optimize extraction flows.
  • Collaborate with design teams to integrate extraction methodologies into the overall IC design flow.
  • Write and maintain scripts in Tcl and Python to automate extraction processes and improve workflow efficiency.
  • Conduct thorough analysis and troubleshooting of extraction-related issues to ensure high-quality design outputs.
  • Stay updated with the latest industry trends and advancements in extraction tools and methodologies.

Qualifications:

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
  • Strong/Solid Background in the CAD Semiconductor area.
  • Deep experience with industry-standard extraction tools such as Synopsys StarRC and Cadence Quantus QRC.
  • Proven experience with SPEF correlation and hierarchical extraction flows/methodologies.
  • Proficiency in scripting languages such as Tcl and Python.
  • Knowledge of IC design, physical design, and electronic design automation (EDA) tools.

Preferred Qualifications:

  •  Experience in post-layout simulation and analysis.
  • Familiarity with timing analysis and signal integrity analysis.



Comments

  1. Anonymous8 June 2024 at 06:33

    Applied and got a call also thanks for sharing

    ReplyDelete
  2. Anonymous9 June 2024 at 21:03

    I cannot apply though LinkedIn bcoz whenever i try to apply through " easy apply" option in LinkedIn it shows some error

    ReplyDelete

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