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Physical Design Methodology Engineer at Texas Instruments

  Hello Dear Readers, Texas Instruments Bangalore has a vacancy for the Physical Design Engineer role. We need an Physical Design Methodology Engineer to join our ATD team. The candidate should have a strong background in back-end design of ASIC/SoC chips. The ideal candidate will have a bachelor’s or master’s degree in Electrical Engineering or a related field. Requirements: 1 - 2 Years of experience in physical design Bachelor’s or master’s degree in Electrical/Electronics Engineering or a related field Strong understanding of physical design principles Must know the basics of floorplan, placement, CTS, routing, ECO, Physical Verification Proficiency in back-end design tools, such as Cadence Genus/Innovus/Tempus/Voltus Excellent problem-solving skills and attention to detail Effective communication and collaboration skills Responsibilities: Synthesis to GDSII Perform full Physical design flow and its verification Work closely with Digital Design and DFT engineers Ensure...
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Product Engineer at Siemens EDA

Hello Dear Readers,

Currently, at Siemens EDA (Siemens Digital Industries Software) vacancy for a Product Engineer role.

Job Duties:

We are seeking a dynamic and professional product engineer (PE), who enjoys multi-tasking in a fast-paced, technical, and friendly environment. In this position, you will be focused on product and deployment scalability of Verification IP products line. In this position, you will be working closely with product development teams, marketing managers, application engineers, and customers. Some domestic and international travel will be required once reasonable.

As a PE you will be defining protocol feature prioritization for the verification IP products to address current and emerging protocols standards. You will be working closely with product development and marketing teams to connect these challenges with Siemens’ current and emerging technical solutions. You will also be guiding customers on creating verification testbench methodologies based on UVM and driving verification IP rollout for new protocols.

Support marketing activities:

The PE will work closely with marketing teams to perform market research, product positioning, and creating supporting presentation materials. You will present and demonstrate the Questa verification IP products in conferences, seminars and events.

Work with customers:

You will be working with multiple customers to understand their challenges in design IP verification. Your ability to maintain customer relationships will help make you effective in this role. Customer-facing activities include product demonstrations, training, evaluations, and competitive benchmarking. The PE plays an active role in developing solutions to solve customer verification problems based on their insight into the customers’ environment.

Ideally, you will be a seasoned Verification Engineer who knows protocol standards and verification methodologies such as UVM.

Additional responsibilities include:

  • Managing technical relationships with Siemens’  existing customer base. 
  • Developing a network of technical relationships at a peer-to-peer level with both our customers and the product engineering teams.
  • Delivering technical presentations, demonstrations, and training to audiences including users, managers, and decision-makers.
  • Influencing product direction by gathering customer requirements and defining the use models which drive the product development and marketing teams
  • Participating in new feature specification, development, and validation process to ensure the product will meet customer requirements.

Job Qualifications:

  • At least 2-4 year ASIC and/or FPGA design experience including RTL design, functional verification, and debug.
  • Programming experience using Verilog, SystemVerilog and UVM.
  • Understanding of EDA tools, such as Simulation using Questa, VCS, NC, etc.
  • Knowledge of some protocol standards such as PCIe, DDR, Ethernet, 1553, AMBA etc.
  • Strong communication and presentation skills, both written and verbal.
  • Exposure to sales and applications environments is a plus.
  • Occasional travel is required.
  • Education: B.S.E.E or equivalent; M.S.E.E. or equivalent preferred.

Apply Here

Comments

  1. Anonymous22 December 2023 at 23:24

    MTech with one year Internship experience people's are allowed?

    ReplyDelete

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