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RTL Design Engineer at Skyroot Aerospace

Hello, Dear Readers, Skyroot Aerospace has a vacancy for the RTL Design Engineer role. About Skyroot Aerospace: A cutting-edge startup founded by ex-ISRO scientists. Dedicated to affordable space access, we're rewriting aerospace technology rules. Our dynamic team fosters inventiveness, collaboration, and relentless excellence. Join us on a transformative journey to redefine space possibilities. Welcome to the forefront of space innovation with Skyroot Aerospace! Purpose of role: Understand architectural requirements and Design micro-architecture, implement design blocks using VHDL/Verilog for FPGA based Avionics packages for orbital launch vehicles and ground infrastructure. Job Requirements: 2+ Years of RTL and system design experience. Strong knowledge on Digital System Design (DSD). Strong knowledge of RTL/SoC design/integration with VHDL/Verilog. Strong knowledge in problem solving and debugging skills. Ability to understand architectural requirements and Design micro-archite...
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Inputs to the STA tool

Dear Readers,  

Today we will be discussing the inputs needed for the STA tool and the importance of each input file and its contents. This will be a lengthy and informative presentation. I hope this learning is enjoyable for you all.

Inputs for the STA tool

1. Gate level netlist

2. SDC (Synopsys Design Constraints)

3. .Lib

4. SPEF (Standard Parasitic Exchange Format)

5. SDF (Standard Delay format)


1. Gate level netlist: 

    The tool will receive the netlist after routing as input. Our design information and its connections, including metals and vias, can be found here.

2. SDC: 

    To ensure that the design meets its timing requirements, clock constraints are required in SDC. The contents of SDC include clock-related information such as clock period, clock latency, uncertainty, and transitions. And IO delay modelling like input and output delays, load, max fanout, max capacitance and max transition etc.., we will discuss the SDC contents in detail in the next post including the commands.

3. Lib:  

.Lib contains the following information.

  1. Cell Definitions:

    • Logical Cells: Information about logical standard cells (gates, flip-flops, latches, etc.) and their functionality.
    • I/O Cells: Definitions for input and output cells that interface with the external environment.

  2. Timing Information:

    • Cell Timing Models: Timing characteristics for each standard cell, including delays, transition times, setup times, hold times, etc.
    • Library Constraints: Maximum and minimum input/output arrival times, clock-to-Q delays, and other timing constraints.

  3. Power Information:

    • Power Models: Power consumption information for each standard cell, including dynamic power, leakage power, and total power.

  4. Physical Information:

    • Cell Area Models: Information about the physical size or area of each standard cell.
    • Pin Placement: Location and arrangement of pins for each cell.

  5. Voltage and Temperature Dependencies:

    • Voltage Scaling Information: How cell characteristics vary with different supply voltages.
    • Temperature Scaling Information: How cell characteristics vary with different temperatures.

  6. Library Constraints:

    • Maximum Capacitance: Maximum allowable load capacitance for each cell.
    • Maximum Fanout: Maximum number of loads a cell can drive.

  7. Other Information:

    • Library Version Information: Details about the library version and compatibility.
    • Corner Models: Different corners representing best-case, typical, and worst-case scenarios for process variations.
    • Please keep in mind that this is a simplified example for illustrative purposes, and the actual '.lib' files are much more detailed and complex.

# Header Information
library(example_lib) {
  technology (CMOS);
  voltage (3.3);
  time_unit : ns;
  capacitance_unit (1e-15);
  current_unit : mA;
  leakage_power_unit : nW;
  library_features (cell);

  # Logical Cell Definitions
  cell(nand2) {
    area : 4.5;   # Cell area in square micrometers
    cell_leakage_power : 10;   # Leakage power in nW
    cell_footprint : "AND2_X1";   # Physical footprint

    # Timing Models
    cell_fall(delay_template) {
      values(1.0, 2.0, 3.0);   # Timing values for falling transition
    }
    cell_rise(delay_template) {
      values(1.5, 2.5, 3.5);   # Timing values for rising transition
    }

    # Power Models
    cell_power(dynamic) {
      when : "A";
      values(0.5, 1.0, 1.5);   # Dynamic power values
    }
    cell_power(leakage) {
      values(5.0);   # Static or leakage power value
    }

    # Pin Information
    pin(A) {
      direction : input;
      capacitance : 0.1;   # Input capacitance
    }
    pin(B) {
      direction : input;
      capacitance : 0.1;
    }
    pin(Y) {
      direction : output;
      capacitance : 0.2;   # Output capacitance
    }
  }
}
    • 4. SPEF :
    This file was extracted from the layout using Star RC extraction tool (Synopsys), which contains parasitic information of interconnects. These include resistances and capacitances associated with the wires and vias, which are essential for STA timing calculations and also for estimating signal integrity and power consumption. The capacitance affects the speed of the signal transition and is crucial for estimating dynamic power consumption. These values were generated at different temperatures for every corner (the best, worst, and typical values of R, C, and RC). Every net has a unique ID corresponding to R,C values.
  1. Here's a simplified example of what a SPEF file might look like:

      2. * Unit: 1.0E-12 F, 1.0E+3 Ohms * Design Information Section D_NET 1 CLK * Node Information Section * Format: (node name) (node capacitance) (node resistance) * Units: F Ohms * Example: * R 1 1.0 * C 1 0.5 * Resistances and Capacitances Section * Format: (net name) (capacitance between nodes) (resistance between nodes) * Units: F Ohms * Example: * * 2 1.0 0.5
5. SDF :

    This contains back annotated information describes cell delays, interconnect delays, timing checks. The timing checks includes setup, hold, recovery time, removal time, minimum pulse width. Some engineers won't give SDF as an input to the STA tool, but this can be useful for DFT engineers then PD engineer has to generate SDF by using "write_sdf" command and give it to them.
  1. To get a sense of how the SDF file would look, the following example is very basic. The actual file will be vast and complex.

  5. ;; Cell Timing Section
  6. (cell (cell_name)
  7.   (cell_rise (condition) (timing_value))
  8.   (cell_fall (condition) (timing_value))
  9.   ; ... other cell timing information ...
  10. )

  12. ;; Pin Timing Section
  13. (pin (cell_name) (pin_name)
  14.   (rise_capacitance (condition) (capacitance_value))
  15.   (fall_capacitance (condition) (capacitance_value))
  16.   ; ... other pin timing information ...
  17. )

  19. ;; Timing Checks Section
  20. (check (cell_name) (check_type) (limit_value))
  21. ; ... other timing checks ...

  23. ;; Port Transition Section
  24. (port (port_name) (clock_transition (rise|fall) (transition_value)))
  25. ; ... other port transition information ...

  27. ;; Interconnect Timing Section
  28. (interconnect (from_pin) (to_pin)
  29.   (rise_delay (condition) (delay_value))
  30.   (fall_delay (condition) (delay_value))
  31.   ; ... other interconnect timing information ...
  32. )

  34. ;; Clock Section
  35. (clock (clock_name)
  36.   (clock_type (primary|generated))
  37.   (period (condition) (period_value))
  38.   ; ... other clock information ...
  39. )

  41. ;; Clock Network Section
  42. (clock_network (clock_name)
  43.   (hierarchical_pin_name (port_name))
  44.   ; ... other clock network information ...
  45. )

STA SERIES:




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