Skip to main content

Physical Design Methodology Engineer at Texas Instruments

  Hello Dear Readers, Texas Instruments Bangalore has a vacancy for the Physical Design Engineer role. We need an Physical Design Methodology Engineer to join our ATD team. The candidate should have a strong background in back-end design of ASIC/SoC chips. The ideal candidate will have a bachelor’s or master’s degree in Electrical Engineering or a related field. Requirements: 1 - 2 Years of experience in physical design Bachelor’s or master’s degree in Electrical/Electronics Engineering or a related field Strong understanding of physical design principles Must know the basics of floorplan, placement, CTS, routing, ECO, Physical Verification Proficiency in back-end design tools, such as Cadence Genus/Innovus/Tempus/Voltus Excellent problem-solving skills and attention to detail Effective communication and collaboration skills Responsibilities: Synthesis to GDSII Perform full Physical design flow and its verification Work closely with Digital Design and DFT engineers Ensure...
Post a Comment

Inputs to the STA tool

Dear Readers,  

Today we will be discussing the inputs needed for the STA tool and the importance of each input file and its contents. This will be a lengthy and informative presentation. I hope this learning is enjoyable for you all.

Inputs for the STA tool

1. Gate level netlist

2. SDC (Synopsys Design Constraints)

3. .Lib

4. SPEF (Standard Parasitic Exchange Format)

5. SDF (Standard Delay format)


1. Gate level netlist: 

    The tool will receive the netlist after routing as input. Our design information and its connections, including metals and vias, can be found here.

2. SDC: 

    To ensure that the design meets its timing requirements, clock constraints are required in SDC. The contents of SDC include clock-related information such as clock period, clock latency, uncertainty, and transitions. And IO delay modelling like input and output delays, load, max fanout, max capacitance and max transition etc.., we will discuss the SDC contents in detail in the next post including the commands.

3. Lib:  

.Lib contains the following information.

  1. Cell Definitions:

    • Logical Cells: Information about logical standard cells (gates, flip-flops, latches, etc.) and their functionality.
    • I/O Cells: Definitions for input and output cells that interface with the external environment.

  2. Timing Information:

    • Cell Timing Models: Timing characteristics for each standard cell, including delays, transition times, setup times, hold times, etc.
    • Library Constraints: Maximum and minimum input/output arrival times, clock-to-Q delays, and other timing constraints.

  3. Power Information:

    • Power Models: Power consumption information for each standard cell, including dynamic power, leakage power, and total power.

  4. Physical Information:

    • Cell Area Models: Information about the physical size or area of each standard cell.
    • Pin Placement: Location and arrangement of pins for each cell.

  5. Voltage and Temperature Dependencies:

    • Voltage Scaling Information: How cell characteristics vary with different supply voltages.
    • Temperature Scaling Information: How cell characteristics vary with different temperatures.

  6. Library Constraints:

    • Maximum Capacitance: Maximum allowable load capacitance for each cell.
    • Maximum Fanout: Maximum number of loads a cell can drive.

  7. Other Information:

    • Library Version Information: Details about the library version and compatibility.
    • Corner Models: Different corners representing best-case, typical, and worst-case scenarios for process variations.
    • Please keep in mind that this is a simplified example for illustrative purposes, and the actual '.lib' files are much more detailed and complex.

# Header Information
library(example_lib) {
  technology (CMOS);
  voltage (3.3);
  time_unit : ns;
  capacitance_unit (1e-15);
  current_unit : mA;
  leakage_power_unit : nW;
  library_features (cell);

  # Logical Cell Definitions
  cell(nand2) {
    area : 4.5;   # Cell area in square micrometers
    cell_leakage_power : 10;   # Leakage power in nW
    cell_footprint : "AND2_X1";   # Physical footprint

    # Timing Models
    cell_fall(delay_template) {
      values(1.0, 2.0, 3.0);   # Timing values for falling transition
    }
    cell_rise(delay_template) {
      values(1.5, 2.5, 3.5);   # Timing values for rising transition
    }

    # Power Models
    cell_power(dynamic) {
      when : "A";
      values(0.5, 1.0, 1.5);   # Dynamic power values
    }
    cell_power(leakage) {
      values(5.0);   # Static or leakage power value
    }

    # Pin Information
    pin(A) {
      direction : input;
      capacitance : 0.1;   # Input capacitance
    }
    pin(B) {
      direction : input;
      capacitance : 0.1;
    }
    pin(Y) {
      direction : output;
      capacitance : 0.2;   # Output capacitance
    }
  }
}
    • 4. SPEF :
    This file was extracted from the layout using Star RC extraction tool (Synopsys), which contains parasitic information of interconnects. These include resistances and capacitances associated with the wires and vias, which are essential for STA timing calculations and also for estimating signal integrity and power consumption. The capacitance affects the speed of the signal transition and is crucial for estimating dynamic power consumption. These values were generated at different temperatures for every corner (the best, worst, and typical values of R, C, and RC). Every net has a unique ID corresponding to R,C values.
  1. Here's a simplified example of what a SPEF file might look like:

      2. * Unit: 1.0E-12 F, 1.0E+3 Ohms * Design Information Section D_NET 1 CLK * Node Information Section * Format: (node name) (node capacitance) (node resistance) * Units: F Ohms * Example: * R 1 1.0 * C 1 0.5 * Resistances and Capacitances Section * Format: (net name) (capacitance between nodes) (resistance between nodes) * Units: F Ohms * Example: * * 2 1.0 0.5
5. SDF :

    This contains back annotated information describes cell delays, interconnect delays, timing checks. The timing checks includes setup, hold, recovery time, removal time, minimum pulse width. Some engineers won't give SDF as an input to the STA tool, but this can be useful for DFT engineers then PD engineer has to generate SDF by using "write_sdf" command and give it to them.
  1. To get a sense of how the SDF file would look, the following example is very basic. The actual file will be vast and complex.

  5. ;; Cell Timing Section
  6. (cell (cell_name)
  7.   (cell_rise (condition) (timing_value))
  8.   (cell_fall (condition) (timing_value))
  9.   ; ... other cell timing information ...
  10. )

  12. ;; Pin Timing Section
  13. (pin (cell_name) (pin_name)
  14.   (rise_capacitance (condition) (capacitance_value))
  15.   (fall_capacitance (condition) (capacitance_value))
  16.   ; ... other pin timing information ...
  17. )

  19. ;; Timing Checks Section
  20. (check (cell_name) (check_type) (limit_value))
  21. ; ... other timing checks ...

  23. ;; Port Transition Section
  24. (port (port_name) (clock_transition (rise|fall) (transition_value)))
  25. ; ... other port transition information ...

  27. ;; Interconnect Timing Section
  28. (interconnect (from_pin) (to_pin)
  29.   (rise_delay (condition) (delay_value))
  30.   (fall_delay (condition) (delay_value))
  31.   ; ... other interconnect timing information ...
  32. )

  34. ;; Clock Section
  35. (clock (clock_name)
  36.   (clock_type (primary|generated))
  37.   (period (condition) (period_value))
  38.   ; ... other clock information ...
  39. )

  41. ;; Clock Network Section
  42. (clock_network (clock_name)
  43.   (hierarchical_pin_name (port_name))
  44.   ; ... other clock network information ...
  45. )

STA SERIES:




Connect with me 


Labels:

Comments

Post a Comment

Popular posts from this blog

Apprenticeship CAI at MediaTek Bangalore

Hello Dear Readers,   Currently at MediaTek Bangalore vacancy for an Apprenticeship CAI role. Job Description: B.Tech degree in Electrical/Electronics Engineering with a strong educational background in Digital circuit design Experience in physical design of high performance design with frequencies > 2 Ghz. Experienced in hierarchical design, budgeting, multiple voltage domains and multiple clock domains. Strong skills with Cadence Encounter. Solid understanding of STA and timing constraints. Experienced in working on advanced process nodes (16nm). Strong expertise in Physical Verification to debug LVS/DRC issues at the block level. Requirement: B.Tech degree in Electrical/Electronics Engineering with strong educational background in Digital circuit design Experience in physical design of high performance design with frequencies > 2 Ghz. Experienced in hierarchical design, budgeting, multiple voltage domains and multiple clock domains. Strong skills with Cadence Enc...
Post a Comment
Read more

IC Physical Design (PnR) at Ulkasemi

Hello Dear Readers,   Ulkasemi  has a vacancy for an IC Physical Design (PnR) role. Job Overview: As a full-time Trainee Engineer, the individual will be working on IC Physical Design implementation from RTL to GDSII to create design databases ready for manufacturing with a special focus on power, performance & area optimization with next-generation state-of-the-art process technologies. Job Responsibilities: Perform physical design implementation which includes Floor planning, Power Planning, Clock Tree Synthesis, Place and Route, ECO, Logic Equivalence checks Timing analysis, physical & electrical verification, driving the sign-off closure meeting schedule, and design goals Develop flow, methodologies, and automation scripts for various implementation steps Follow the instructions, compile documents, prepare deliverables, and report to the team lead Should remain up to date with the latest technology trends Educational Qualification:   B.Sc/M.Sc   in EEE or...
Post a Comment
Read more

Best Book for Designing Microarchitecture of Microprocessor Using Verilog HDL

  Hello Dear Readers, Currently, after succeeding in many topics now I starting to provide technical book reviews which were I have completed and still read books always. So let us start today's book review. Book Name:   Computer Principles and Design in Verilog  HDL Description:  Uses Verilog HDL to illustrate computer architecture and microprocessor design, allowing readers to readily simulate and adjust the operation of each design, and thus build industrially relevant skills Introduces the computer principles, computer design, and how to use Verilog HDL (Hardware Description Language) to implement the design Provides the skills for designing processor/arithmetic/cpu chips, including the unique application of Verilog HDL material for CPU (central processing unit) implementation Despite the many books on Verilog and computer architecture and microprocessor design, few, if any, use Verilog as a key tool in helping a student to understand these design techniques...
3 comments
Read more