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Dear Readers,
Today, we will be talking about STA, which is commonly referred to as static timing analysis. What is the actual meaning of it? What is the reason for doing it? What is the role of STA engineers in the real world? Many of us know that physical design is vast, and placing macros and standard cells interconnected with some metal layers is not enough. It's important to ensure that the input data gets to the output on time without any corruption or overwriting. For that, we need to do Setup and hold checks. What are these setup and hold? What are the reasons behind these timing violations? What is crosstalk, noise, timing arc, and unateness? What are the signoff checks we (STA engineers) do before the chip is going to tape out? All of these concepts we will discuss under this STA topic one by one in detail. Please stay tuned. Continue to read and learn with us. It's going to be fun😇
What is static timing analysis (STA)?
Timing analysis is the evaluation of a design for timing issues, and it is called static because it doesn't involve any input or output vectors. On the contrary, verifying the functionality of the design by giving some test vectors is called dynamic timing analysis. However, increased test vectors result in complex computations and maximum delay. Even though STA is more effective it has some limitations. such as It is not suitable for asynchronous clock domain crossings and unknown logic values(inputs with don't care conditions), STA is subjected to only RTL (Register Transfer Logic) designs, etc... In the future, we will study these limitations in depth.
The most commonly used tools for STA are primetime from Synopsys Primetime user guide and tempus from cadence Tempus user guide.
Why STA?
Verification of timing through simulations by applying test vectors is very exhaustive and time-consuming. As we know one chip contains billions of gates verify the timing for these using simulations is very slow. That's where STA will help, it is the faster and simplest way to analyze the timing in the most pessimistic way. And also the effects of crosstalk, noise, and on-chip variations cannot be handled by logic simulation-based verification.
What actually STA does?
It breaks the design into timing paths, each path has a start and end point. The net delays and cell delays are added to calculate the timing for each path. Then the tool analyzes these paths and checks whether they meet our timing requirement.
In industry, at different stages of implementation STA will be performed. This will be shown in the below figure.
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