Skip to main content

Posts

Showing posts from December, 2023

Verification Engineer or Senior Verification Engineer SOC at MIPS India

Hello Dear Readers, Currently, at MIPS India  vacancy for a Verification Engineer or Senior Verification Engineer SOC role. We are seeking an experienced Verification Engineer or Senior Verification Engineer SOC. This position involves extensive hands-on experience with CPU verification using industry-standard functional verification methodologies, formal verification, and constrained random generators, and reference model-based checkers. The candidate must be able to take critical decisions and completely own verification closure for a block or feature. This position involves cross-functional interaction with CPU designers and architects and working across sites to ensure high-quality CPU designs for customers. You will: Take full ownership and drive verification efforts to closure Work closely with designers and architects to understand specifications at unit/top level Understand use cases and develop functional test plans Develop directed tests written in C, Assembly, and SystemVeri
Post a Comment
Read more

Jr. ASIC Verification Engineer at Smart Chip Design

Hello Dear Readers, Currently, at Smart Chip Design vacancy for a Jr. ASIC Verification Engineer role. Smart Chip Design is a provider of VLSI (Very Large Scale Integration) training courses and advanced VLSI design in Bengaluru, Karnataka. We strive to offer the best training programs in the industry, in addition to delivering top-quality design services. Our mission is to empower engineers with the skills and expertise they need to create innovative and cutting-edge products that can make a difference in the world. Role Description: This is a full-time remote role for a Jr. ASIC verification engineer. The Jr. ASIC (Application-Specific Integrated Circuit) Verification Engineer will be responsible for ensuring the correctness of complex ASIC designs through a variety of tools and methodologies. The engineer will collaborate with cross-functional teams to identify issues and provide customized solutions and will work closely with designers and other verification engineers to create ef
Post a Comment
Read more

FPGA/RTL Interns at Morphing Machines Private Limited

Hello Dear Readers, Currently, at Morphing Machines Private Limited vacancy for an FPGA/RTL Intern role. Job Overview: We are seeking a highly motivated FPGA/RTL Intern to join our dynamic team. This internship offers a unique opportunity to gain hands-on experience in the field of FPGA/RTL development. The intern will work closely with our engineering team on cutting-edge projects and contribute to the design and implementation of FPGA solutions. Key Responsibilities: FPGA Design: Assist in the design and development of FPGA-based solutions for specific applications and projects under the guidance of senior FPGA design engineers. RTL Coding: Write and optimize RTL (Register Transfer Level) code using hardware description languages (HDL) such as Verilog or VHDL. Simulation: Conduct RTL simulations to verify the correctness of the RTL design and ensure it meets the required specifications. Synthesis & Implementation: Work with FPGA synthesis tools to convert RTL code into an FPGA bi
1 comment
Read more

SDC (Synopsys Design Constraints) contents part 2

 Dear readers, This is the continuation of SDC contents. Today we will talk about other clock related attributes such as clock latency, uncertainty. 3. set_clock_latency     Latency is the delay taken by a clock signal to reach the clock pin of a register from the clock source. This delay can be added by clock buffers and parasitic on the net. It is of two types. Source latency and Network latency.       Source latency is the delay from the clock source to the clock definition point. This is also called insertion  delay. This could represent either on-chip or off-chip. Network latency is the delay from clock definition point to clock pin of a flipflop. Therefore, Clock latency = Source latency + Network latency. This is shown in below figure for on-chip and off-chip.      Network latency is an estimated delay before clock tree is built in CTS stage. Once clock tree is built this is ignored and actual delay came into picture. However, source latency is same even after CTS stage.     
Post a Comment
Read more

Product Engineer at Siemens EDA

Hello Dear Readers, Currently, at  Siemens EDA (Siemens Digital Industries Software)  vacancy for a Product Engineer role. Job Duties: We are seeking a dynamic and professional product engineer (PE), who enjoys multi-tasking in a fast-paced, technical, and friendly environment. In this position, you will be focused on product and deployment scalability of Verification IP products line. In this position, you will be working closely with product development teams, marketing managers, application engineers, and customers. Some domestic and international travel will be required once reasonable. As a PE you will be defining protocol feature prioritization for the verification IP products to address current and emerging protocols standards. You will be working closely with product development and marketing teams to connect these challenges with Siemens’ current and emerging technical solutions. You will also be guiding customers on creating verification testbench methodologies based on UVM a
1 comment
Read more

SDC (Synopsys Design constraints) contents part 1

       Dear readers, Today we will talk about the contents of the SDC, including commands. Concepts of skew, latency, uncertainty and more. However, since this might get lengthy, we will only cover a few of them here, covering the rest in later posts. Hope you guys have fun reading it. In order to execute STA on the design, you will need to specify the clock for the flipflops and timing restrictions for all the ways in the design and all the ways out of the design. Clock Attributes 1. create_clock        This creates a clock in the current design at the declared source and defines its period and waveform. The STA uses this information to propagate the waveform across the clock network to the clock pins of all sequential elements driven by this clock source. This is also called master clock.      Ex1: create_clock -period 10 -waveform{0 5} -name CLK [get_ports SCLK] - name of the clock is CLK having period of 10ns with rising edge at 0ns and falling edge at 5ns is defined at the port
Post a Comment
Read more

Inputs to the STA tool

Dear Readers,    Today we will be discussing the inputs needed for the STA tool and the importance of each input file and its contents. This will be a lengthy and informative presentation. I hope this learning is enjoyable for you all. Inputs for the STA tool 1. Gate level netlist 2. SDC (Synopsys Design Constraints) 3. .Lib 4. SPEF (Standard Parasitic Exchange Format) 5. SDF (Standard Delay format) 1. Gate level netlist:       The tool will receive the netlist after routing as input. Our design information and its connections, including metals and vias, can be found here. 2. SDC:        To ensure that the design meets its timing requirements, clock constraints are required in SDC. The contents of SDC include clock-related information such as clock period, clock latency, uncertainty, and transitions. And IO delay modelling like input and output delays, load, max fanout, max capacitance and max transition etc.., we will discuss the SDC contents in detail in the next post including the c
1 comment
Read more