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RTL Design Engineer at Skyroot Aerospace

Hello, Dear Readers, Skyroot Aerospace has a vacancy for the RTL Design Engineer role. About Skyroot Aerospace: A cutting-edge startup founded by ex-ISRO scientists. Dedicated to affordable space access, we're rewriting aerospace technology rules. Our dynamic team fosters inventiveness, collaboration, and relentless excellence. Join us on a transformative journey to redefine space possibilities. Welcome to the forefront of space innovation with Skyroot Aerospace! Purpose of role: Understand architectural requirements and Design micro-architecture, implement design blocks using VHDL/Verilog for FPGA based Avionics packages for orbital launch vehicles and ground infrastructure. Job Requirements: 2+ Years of RTL and system design experience. Strong knowledge on Digital System Design (DSD). Strong knowledge of RTL/SoC design/integration with VHDL/Verilog. Strong knowledge in problem solving and debugging skills. Ability to understand architectural requirements and Design micro-archite...
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SDC (Synopsys Design Constraints) contents part 2

 Dear readers, This is the continuation of SDC contents. Today we will talk about other clock related attributes such as clock latency, uncertainty.


3. set_clock_latency

    Latency is the delay taken by a clock signal to reach the clock pin of a register from the clock source. This delay can be added by clock buffers and parasitic on the net. It is of two types. Source latency and Network latency. 

    Source latency is the delay from the clock source to the clock definition point. This is also called insertion  delay. This could represent either on-chip or off-chip. Network latency is the delay from clock definition point to clock pin of a flipflop.

Therefore, Clock latency = Source latency + Network latency.

This is shown in below figure for on-chip and off-chip.


    Network latency is an estimated delay before clock tree is built in CTS stage. Once clock tree is built this is ignored and actual delay came into picture. However, source latency is same even after CTS stage.

    Ex: set_clock_latency  1.2  -source [get_clocks CLK]    ------> source latency

         set_clock_latency 0.6 [get_clocks CLK_CONFIG]     ------>Network latency

 Observe, network latency is specified without '-source' option.

 4. set_clock_uncertainty

Uncertainty used to model the various factors that reduces the effective clock period. Those factors includes skew, jitter or any other pessimism. Setup uncertainty reduces the effective clock period and hold uncertainty used as additional timing margin that needs to be satisfied. That is it pushes the hold requirement further. 

    Ex: set_clock_uncertainty -setup 0.3 [get_clocks CLK_CONFIG]

            set_clock_uncertainty -hold 0.05 [get_clocks CLK_CONFIG]





SKEW: 

It is the time difference between the arrival of clocks at the clock pins of a flip-flop. 

                    Tskew  = Tcapture - Tlaunch 

Positive Skew if Tcapture > Tlaunch                 It is good for set up violation

Negative Skew if Tcapture < Tlaunch               It is good for hold violation   (we will discuss more                                                                                                            about this in future posts)

Note that skew can be seen between the same clock domain or between the different clock domains as well. It is hard to write everything here, like it is very huge topic there are various factors that causes skew internally and externally. So, I am trying to explain here as much simple as possible.

If the difference between arrival time of clock signals at two registers (both registers are of same clock domain) then that is called Intra clock skew or Local skew. If the registers are clocked by different clock domain then that time difference is called Inter clock skew or global skew. Global skew is also defined as difference between longest path delay and shortest path delay on a clock tree. There are multiple definitions for global skew, In general global skew refers to the difference between the clock arrival times across the entire IC. Following figure will give you a clear picture of this.


Skew between FF1 and FF2 is Local skew or intra clock skew.

Skew between FF1 and FF3 is global skew or inter clock skew.

 

we will discuss IO constraints in the next article. Thanks for reading this blog.

I know you guys are eagerly waiting for setup and hold concepts. I will post about that after SDC contents. There are many other concepts in STA we will discuss about that too in our future posts.






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