Skip to main content

Design Engineer - STA, SD, Power, PDN at Dew Software

Hello Dear Readers,   Currently at Dew Software Bangalore vacancy for Design Engineer - STA, SD, Power, PDN role. Dew Software, a leading player in the Digital Transformation space, is seeking a skilled Design Engineer specializing in STA (Static Timing Analysis), SD (Signal Integrity), Power, and PDN (Power Delivery Network) to join our team. Working with Fortune 500 companies to support their digital innovation and transformation strategies, the Design Engineer will be responsible for ensuring the integrity and efficiency of digital designs through comprehensive analysis and optimization. Dew Software is dedicated to delivering exceptional outcomes with cutting-edge technologies, and this is an excellent opportunity to contribute to the growth and success of our clients. Responsibilities: Perform STA (Static Timing Analysis) to ensure design meets timing requirements Conduct signal integrity analysis to optimize signal integrity and minimize signal integrity issues Provide power anal

FPGA/RTL Interns at Morphing Machines Private Limited

Hello Dear Readers,

Currently, at Morphing Machines Private Limited vacancy for an FPGA/RTL Intern role.


Job Overview:

We are seeking a highly motivated FPGA/RTL Intern to join our dynamic team. This internship offers a unique opportunity to gain hands-on experience in the field of FPGA/RTL development. The intern will work closely with our engineering team on cutting-edge projects and contribute to the design and implementation of FPGA solutions.

Key Responsibilities:

  • FPGA Design: Assist in the design and development of FPGA-based solutions for specific applications and projects under the guidance of senior FPGA design engineers.
  • RTL Coding: Write and optimize RTL (Register Transfer Level) code using hardware description languages (HDL) such as Verilog or VHDL.
  • Simulation: Conduct RTL simulations to verify the correctness of the RTL design and ensure it meets the required specifications.
  • Synthesis & Implementation: Work with FPGA synthesis tools to convert RTL code into an FPGA bit file. Develop build scripts to automate the process.
  • Verification & Testing: Support the verification and testing of FPGA designs through testbench development and test case execution.
  • Debugging: Collaborate with the team to identify and resolve design issues using simulation and logic analyzer tools.
  • Documentation: Create and maintain prototype design documentation, including design specifications, test plans, and reports.
  • Learning & Training: Take part in internal training sessions and workshops to enhance knowledge and skills in FPGA design and related technologies.
  • Collaborative Projects: Participate in group projects and contribute to the overall success of the FPGA design team.
  • Innovation: Contribute ideas and suggestions to improve design methodologies, tools, and workflows.

Qualifications and Skills:

  • Currently pursuing a Bachelor's or Master's degree in Electrical/Electronics Engineering, Computer Engineering, or related fields with a focus on digital design or FPGA.
  • Basic understanding of digital design concepts and hardware description languages (Verilog, VHDL).
  • Familiarity with FPGA development tools and environments is a plus but not mandatory.
  • Hands-on experience with FPGA development boards or embedded systems is advantageous.
  • Solid problem-solving skills and the ability to analyze and debug hardware designs.
  • Strong written and verbal communication skills.
  • Eagerness to learn and collaborate in a team-oriented environment.
  • Familiarity with scripting languages (Python, Perl, etc.) is a plus.

Comments

  1. Dear Sir I am selected for this position. Thanks for your guidance about resume building.

    ReplyDelete

Post a Comment

Popular posts from this blog

Apprenticeship CAI at MediaTek Bangalore

Hello Dear Readers,   Currently at MediaTek Bangalore vacancy for an Apprenticeship CAI role. Job Description: B.Tech degree in Electrical/Electronics Engineering with a strong educational background in Digital circuit design Experience in physical design of high performance design with frequencies > 2 Ghz. Experienced in hierarchical design, budgeting, multiple voltage domains and multiple clock domains. Strong skills with Cadence Encounter. Solid understanding of STA and timing constraints. Experienced in working on advanced process nodes (16nm). Strong expertise in Physical Verification to debug LVS/DRC issues at the block level. Requirement: B.Tech degree in Electrical/Electronics Engineering with strong educational background in Digital circuit design Experience in physical design of high performance design with frequencies > 2 Ghz. Experienced in hierarchical design, budgeting, multiple voltage domains and multiple clock domains. Strong skills with Cadence Encounter. Solid

Power Analysis in the VLSI Chip Design

  Hello Dear Readers,   Today in this series of posts I will provide some deep insight into Power Analysis in the VLSI Chip Design. The power analysis flow calculates (estimates of) the active and static leakage power dissipation of the SoC design. This electrical analysis step utilizes the detailed extraction model of the block and global SoC layouts. The active power estimates depend on the availability of switching factors for all signals in the cell netlist. Representative simulation test cases are applied to the netlist model, and the signal value change data are recorded. The output data from the power analysis flow guide the following SoC tape out release assessments:  Total SoC power specification (average and standby leakage): The specification for SoC power is critical for package selection and is used by end customers for thermal analysis of the product enclosure. In addition to the package technology selection, the SoC power dissipation is used to evaluate the die attach ma

IC Physical Design (PnR) at Ulkasemi

Hello Dear Readers,   Ulkasemi  has a vacancy for an IC Physical Design (PnR) role. Job Overview: As a full-time Trainee Engineer, the individual will be working on IC Physical Design implementation from RTL to GDSII to create design databases ready for manufacturing with a special focus on power, performance & area optimization with next-generation state-of-the-art process technologies. Job Responsibilities: Perform physical design implementation which includes Floor planning, Power Planning, Clock Tree Synthesis, Place and Route, ECO, Logic Equivalence checks Timing analysis, physical & electrical verification, driving the sign-off closure meeting schedule, and design goals Develop flow, methodologies, and automation scripts for various implementation steps Follow the instructions, compile documents, prepare deliverables, and report to the team lead Should remain up to date with the latest technology trends Educational Qualification:   B.Sc/M.Sc   in EEE or equivalent degree