Skip to main content

Verification Engineer or Senior Verification Engineer SOC at MIPS India

Hello Dear Readers, Currently, at MIPS India  vacancy for a Verification Engineer or Senior Verification Engineer SOC role. We are seeking an experienced Verification Engineer or Senior Verification Engineer SOC. This position involves extensive hands-on experience with CPU verification using industry-standard functional verification methodologies, formal verification, and constrained random generators, and reference model-based checkers. The candidate must be able to take critical decisions and completely own verification closure for a block or feature. This position involves cross-functional interaction with CPU designers and architects and working across sites to ensure high-quality CPU designs for customers. You will: Take full ownership and drive verification efforts to closure Work closely with designers and architects to understand specifications at unit/top level Understand use cases and develop functional test plans Develop directed tests written in C, Assembly, and SystemVeri
Post a Comment

FPGA/RTL Interns at Morphing Machines Private Limited

Hello Dear Readers,

Currently, at Morphing Machines Private Limited vacancy for an FPGA/RTL Intern role.


Job Overview:

We are seeking a highly motivated FPGA/RTL Intern to join our dynamic team. This internship offers a unique opportunity to gain hands-on experience in the field of FPGA/RTL development. The intern will work closely with our engineering team on cutting-edge projects and contribute to the design and implementation of FPGA solutions.

Key Responsibilities:

  • FPGA Design: Assist in the design and development of FPGA-based solutions for specific applications and projects under the guidance of senior FPGA design engineers.
  • RTL Coding: Write and optimize RTL (Register Transfer Level) code using hardware description languages (HDL) such as Verilog or VHDL.
  • Simulation: Conduct RTL simulations to verify the correctness of the RTL design and ensure it meets the required specifications.
  • Synthesis & Implementation: Work with FPGA synthesis tools to convert RTL code into an FPGA bit file. Develop build scripts to automate the process.
  • Verification & Testing: Support the verification and testing of FPGA designs through testbench development and test case execution.
  • Debugging: Collaborate with the team to identify and resolve design issues using simulation and logic analyzer tools.
  • Documentation: Create and maintain prototype design documentation, including design specifications, test plans, and reports.
  • Learning & Training: Take part in internal training sessions and workshops to enhance knowledge and skills in FPGA design and related technologies.
  • Collaborative Projects: Participate in group projects and contribute to the overall success of the FPGA design team.
  • Innovation: Contribute ideas and suggestions to improve design methodologies, tools, and workflows.

Qualifications and Skills:

  • Currently pursuing a Bachelor's or Master's degree in Electrical/Electronics Engineering, Computer Engineering, or related fields with a focus on digital design or FPGA.
  • Basic understanding of digital design concepts and hardware description languages (Verilog, VHDL).
  • Familiarity with FPGA development tools and environments is a plus but not mandatory.
  • Hands-on experience with FPGA development boards or embedded systems is advantageous.
  • Solid problem-solving skills and the ability to analyze and debug hardware designs.
  • Strong written and verbal communication skills.
  • Eagerness to learn and collaborate in a team-oriented environment.
  • Familiarity with scripting languages (Python, Perl, etc.) is a plus.

Comments

  1. Anonymous26 January 2024 at 22:08

    Dear Sir I am selected for this position. Thanks for your guidance about resume building.

    ReplyDelete

Post a Comment

Popular posts from this blog

SDC (Synopsys Design Constraints) contents part 4

Today, we will be discussing the remaining constraints mentioned in the SDC, which pertain to timing exceptions and design rules. This is the final part of the SDC contents. This is going to be interesting, especially with multicycle paths. Take time to read and try to comprehend. 10. set_max_transition     By setting max transition value, our design checks that all ports and pins are meeting the specified limits mentioned in SDC. If these are not satisfied then timing report will give DRVs (design rule violations) in terms of slack. This is specified as               set_max_transition 0.5  UBUF1/A setting maximum limit of 500ps on pin A of Buffer1. 11. set_max_capacitance     This is same as max transition, setting the maximum capacitance value. if our design not meeting this value then violation will occur. This will also reports under design rule violations in terms of slack.     set_max_capacitance 0.7 [all_nets] setting maximum capacitance of 700fF on all nets. similarly, set_max
1 comment
Read more

Apprenticeship CAI at MediaTek Bangalore

Hello Dear Readers,   Currently at MediaTek Bangalore vacancy for an Apprenticeship CAI role. Job Description: B.Tech degree in Electrical/Electronics Engineering with a strong educational background in Digital circuit design Experience in physical design of high performance design with frequencies > 2 Ghz. Experienced in hierarchical design, budgeting, multiple voltage domains and multiple clock domains. Strong skills with Cadence Encounter. Solid understanding of STA and timing constraints. Experienced in working on advanced process nodes (16nm). Strong expertise in Physical Verification to debug LVS/DRC issues at the block level. Requirement: B.Tech degree in Electrical/Electronics Engineering with strong educational background in Digital circuit design Experience in physical design of high performance design with frequencies > 2 Ghz. Experienced in hierarchical design, budgeting, multiple voltage domains and multiple clock domains. Strong skills with Cadence Encounter. Solid
Post a Comment
Read more

IC Physical Design (PnR) at Ulkasemi

Hello Dear Readers,   Ulkasemi  has a vacancy for an IC Physical Design (PnR) role. Job Overview: As a full-time Trainee Engineer, the individual will be working on IC Physical Design implementation from RTL to GDSII to create design databases ready for manufacturing with a special focus on power, performance & area optimization with next-generation state-of-the-art process technologies. Job Responsibilities: Perform physical design implementation which includes Floor planning, Power Planning, Clock Tree Synthesis, Place and Route, ECO, Logic Equivalence checks Timing analysis, physical & electrical verification, driving the sign-off closure meeting schedule, and design goals Develop flow, methodologies, and automation scripts for various implementation steps Follow the instructions, compile documents, prepare deliverables, and report to the team lead Should remain up to date with the latest technology trends Educational Qualification:   B.Sc/M.Sc   in EEE or equivalent degree
Post a Comment
Read more