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YAML in Semiconductor EDA: From Configuration Language to Reusable Design-Flow Methodology

Hello Dear Readers,   Today in this post, I will provide some deep insight about yaml langauge for CAD flow developments with detailed examples. YAML is not a programming language in the same sense as Python, Tcl, C++, or Verilog. It is primarily a human-readable data serialization/configuration language . In semiconductor EDA, that distinction is important because YAML generally describes what a flow should do , while Python/Tcl/Shell and the EDA tools execute the flow . The official YAML specification describes it as a data serialization language designed to be human-friendly and portable across programming languages. For the semiconductor angle, this becomes particularly interesting because YAML can act as a configuration layer between design methodology and EDA implementation . Frameworks such as Hammer explicitly use YAML/JSON configuration and an intermediate representation to standardize information exchanged between design, technology, and tool plugins. 1. Introduction M...
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SDC (Synopsys Design constraints) contents part 1

Dear readers, Today we will talk about the contents of the SDC, including commands. Concepts of skew, latency, uncertainty and more. However, since this might get lengthy, we will only cover a few of them here, covering the rest in later posts. Hope you guys have fun reading it.

In order to execute STA on the design, you will need to specify the clock for the flipflops and timing restrictions for all the ways in the design and all the ways out of the design.

Clock Attributes

1. create_clock

     This creates a clock in the current design at the declared source and defines its period and waveform. The STA uses this information to propagate the waveform across the clock network to the clock pins of all sequential elements driven by this clock source. This is also called master clock.

    Ex1: create_clock -period 10 -waveform{0 5} -name CLK [get_ports SCLK]

- name of the clock is CLK having period of 10ns with rising edge at 0ns and falling edge at 5ns is defined at the port SCLK. if -name is not specified then the clock name will be same as the port name.

    Ex2: create_clock -period 4 -name VRCLK

    - Above clock has no pins/ports associated with it, that type of clock is called virtual clock. Virtual clock physically does not exist, but it can be used to constrain the clock. It is used as a reference to constrain the interface pins.

2. create_generated_clock

   For suppose if there is a divide-by-2 circuitry for a clock, then the time period of clock will change but STA does not know what the clock period in that case. So, we need to define these clocks as 'generated clocks'. Basically, generated clocks are derived from master clocks. It might be 'multiply-by' or 'divide-by'  1,2 3 etc.., and edge-shift options.

Ex1: create_generated_clock -divide_by 2 -name CLKDIV2 -source CLK [get_pins UPLL/CLKOUT]

 - Here observe, generated clock named CLKDIV2 derived from CLK with period of 20ns is defined at the output of  PLL . Note that 'multiply-by', 'divide-by' options referred to frequency of the clock. In this case frequency is divided by 2 means period will be doubled that is 20ns.  At -source option we can give clock name or clock pin, both will work. below figure will give you a clear idea.


Another example for generated clock is 

Ex2: create_generated_clock -divide_by 1 -name CLKDIV1 -source CLK [get_pins UAND1/Y].

-In the above example, the generated clock period is the same as the master clock period. Then you must have a doubt that do we need to generate another clock, if the clock period is same as the master clock, we can directly fed master clock to the flipflop? The answer is yes, we can create new master clock indeed. However, there are a few problems.  See below example



    In above figure CLK is our master clock, which is gated by a flipflop. But flipflop output may not be stable, one way to handle this situation is define generated clock at the output of AND cell which is identical to master clock. We can define another new master clock, but it will create another clock domain then we need to specify the constraints explicitly for new master clock. If new clock is Generated clock then its constraints are same as master clock, another important point is that clock origin is same for both master and generated clock, so in timing reports the start point is same for both. Thus source latency is automatically included for generated clock. This is the big advantage of creating new clock as generated clock than creating new master clock. Another important drawback of creating new clock at internal pins is that it is forcing the designer to compute the path delays manually.

Ex3: create_generated_clock -edges {2 4 6} -name ECLKDIV2  -source CLK [get_pins UBUFF1/Z]

- Here, generated clock created using '-edges' option. first rising edge is at 2 edge of source clock, falling edge is at 4 edge of source clock, next rising edge at 6 edge of source clock and so on.. it repeats.
this is shown below.

  
The remaining we will discuss in next post. Thanks

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