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Physical Design/PDK methodology Engineer

Hello Dear Readers, At Applied Materials Bangalore, there is a vacancy for a Physical Design/PDK methodology Engineer role. Applied Materials is a global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service cutting-edge equipment that helps our customers manufacture display and semiconductor chips – the brains of devices we use every day. As the foundation of the global electronics industry, Applied enables the exciting technologies that literally connect our world – like AI and IoT. If you want to push the boundaries of materials science and engineering to create next generation technology, join us to deliver material innovation that changes the world.  Key Responsibility: Expertise in PDK enablement and library  validation/automation. Hands-on experience with LVS/Parasitic extraction/standard cell characterization flows and methodologies Design/System level experience with DTCO and ...
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Jr. ASIC Verification Engineer at Smart Chip Design

Hello Dear Readers,

Currently, at Smart Chip Design vacancy for a Jr. ASIC Verification Engineer role.

Smart Chip Design is a provider of VLSI (Very Large Scale Integration) training courses and advanced VLSI design in Bengaluru, Karnataka. We strive to offer the best training programs in the industry, in addition to delivering top-quality design services. Our mission is to empower engineers with the skills and expertise they need to create innovative and cutting-edge products that can make a difference in the world.

Role Description:
This is a full-time remote role for a Jr. ASIC verification engineer. The Jr. ASIC (Application-Specific Integrated Circuit) Verification Engineer will be responsible for ensuring the correctness of complex ASIC designs through a variety of tools and methodologies. The engineer will collaborate with cross-functional teams to identify issues and provide customized solutions and will work closely with designers and other verification engineers to create effective verification strategies.

Qualifications:
  • Bachelor's degree or higher in Electrical Engineering, Computer Science, or a related field
  • Strong experience with ASIC verification using SystemVerilog and UVM
  • Strong proficiency in programming in languages like C and Python
  • Experience with script-based verification including TCL, Perl, or shell scripts
  • Ability to implement, test, and debug complex verification environments
  • Demonstrated ability to debug tests, analyze failures and articulate issues
  • Excellent communication skills and ability to work collaboratively in cross-functional teams
  • Strong analytical and problem-solving skills
  • Experience with verification tools like Questasim/VCS/IUS and debugging tools like Verdi
  • Experience with Digital Design, Functional Verification, and Debug using industry-standard tools



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