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YAML in Semiconductor EDA: From Configuration Language to Reusable Design-Flow Methodology

Hello Dear Readers,   Today in this post, I will provide some deep insight about yaml langauge for CAD flow developments with detailed examples. YAML is not a programming language in the same sense as Python, Tcl, C++, or Verilog. It is primarily a human-readable data serialization/configuration language . In semiconductor EDA, that distinction is important because YAML generally describes what a flow should do , while Python/Tcl/Shell and the EDA tools execute the flow . The official YAML specification describes it as a data serialization language designed to be human-friendly and portable across programming languages. For the semiconductor angle, this becomes particularly interesting because YAML can act as a configuration layer between design methodology and EDA implementation . Frameworks such as Hammer explicitly use YAML/JSON configuration and an intermediate representation to standardize information exchanged between design, technology, and tool plugins. 1. Introduction M...
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Jr. ASIC Verification Engineer at Smart Chip Design

Hello Dear Readers,

Currently, at Smart Chip Design vacancy for a Jr. ASIC Verification Engineer role.

Smart Chip Design is a provider of VLSI (Very Large Scale Integration) training courses and advanced VLSI design in Bengaluru, Karnataka. We strive to offer the best training programs in the industry, in addition to delivering top-quality design services. Our mission is to empower engineers with the skills and expertise they need to create innovative and cutting-edge products that can make a difference in the world.

Role Description:
This is a full-time remote role for a Jr. ASIC verification engineer. The Jr. ASIC (Application-Specific Integrated Circuit) Verification Engineer will be responsible for ensuring the correctness of complex ASIC designs through a variety of tools and methodologies. The engineer will collaborate with cross-functional teams to identify issues and provide customized solutions and will work closely with designers and other verification engineers to create effective verification strategies.

Qualifications:
  • Bachelor's degree or higher in Electrical Engineering, Computer Science, or a related field
  • Strong experience with ASIC verification using SystemVerilog and UVM
  • Strong proficiency in programming in languages like C and Python
  • Experience with script-based verification including TCL, Perl, or shell scripts
  • Ability to implement, test, and debug complex verification environments
  • Demonstrated ability to debug tests, analyze failures and articulate issues
  • Excellent communication skills and ability to work collaboratively in cross-functional teams
  • Strong analytical and problem-solving skills
  • Experience with verification tools like Questasim/VCS/IUS and debugging tools like Verdi
  • Experience with Digital Design, Functional Verification, and Debug using industry-standard tools



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