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Physical Design Methodology Engineer at Texas Instruments

  Hello Dear Readers, Texas Instruments Bangalore has a vacancy for the Physical Design Engineer role. We need an Physical Design Methodology Engineer to join our ATD team. The candidate should have a strong background in back-end design of ASIC/SoC chips. The ideal candidate will have a bachelor’s or master’s degree in Electrical Engineering or a related field. Requirements: 1 - 2 Years of experience in physical design Bachelor’s or master’s degree in Electrical/Electronics Engineering or a related field Strong understanding of physical design principles Must know the basics of floorplan, placement, CTS, routing, ECO, Physical Verification Proficiency in back-end design tools, such as Cadence Genus/Innovus/Tempus/Voltus Excellent problem-solving skills and attention to detail Effective communication and collaboration skills Responsibilities: Synthesis to GDSII Perform full Physical design flow and its verification Work closely with Digital Design and DFT engineers Ensure...
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Jr. ASIC Verification Engineer at Smart Chip Design

Hello Dear Readers,

Currently, at Smart Chip Design vacancy for a Jr. ASIC Verification Engineer role.

Smart Chip Design is a provider of VLSI (Very Large Scale Integration) training courses and advanced VLSI design in Bengaluru, Karnataka. We strive to offer the best training programs in the industry, in addition to delivering top-quality design services. Our mission is to empower engineers with the skills and expertise they need to create innovative and cutting-edge products that can make a difference in the world.

Role Description:
This is a full-time remote role for a Jr. ASIC verification engineer. The Jr. ASIC (Application-Specific Integrated Circuit) Verification Engineer will be responsible for ensuring the correctness of complex ASIC designs through a variety of tools and methodologies. The engineer will collaborate with cross-functional teams to identify issues and provide customized solutions and will work closely with designers and other verification engineers to create effective verification strategies.

Qualifications:
  • Bachelor's degree or higher in Electrical Engineering, Computer Science, or a related field
  • Strong experience with ASIC verification using SystemVerilog and UVM
  • Strong proficiency in programming in languages like C and Python
  • Experience with script-based verification including TCL, Perl, or shell scripts
  • Ability to implement, test, and debug complex verification environments
  • Demonstrated ability to debug tests, analyze failures and articulate issues
  • Excellent communication skills and ability to work collaboratively in cross-functional teams
  • Strong analytical and problem-solving skills
  • Experience with verification tools like Questasim/VCS/IUS and debugging tools like Verdi
  • Experience with Digital Design, Functional Verification, and Debug using industry-standard tools



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