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Physical Design Methodology Engineer at Texas Instruments

  Hello Dear Readers, Texas Instruments Bangalore has a vacancy for the Physical Design Engineer role. We need an Physical Design Methodology Engineer to join our ATD team. The candidate should have a strong background in back-end design of ASIC/SoC chips. The ideal candidate will have a bachelor’s or master’s degree in Electrical Engineering or a related field. Requirements: 1 - 2 Years of experience in physical design Bachelor’s or master’s degree in Electrical/Electronics Engineering or a related field Strong understanding of physical design principles Must know the basics of floorplan, placement, CTS, routing, ECO, Physical Verification Proficiency in back-end design tools, such as Cadence Genus/Innovus/Tempus/Voltus Excellent problem-solving skills and attention to detail Effective communication and collaboration skills Responsibilities: Synthesis to GDSII Perform full Physical design flow and its verification Work closely with Digital Design and DFT engineers Ensure...
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PowerVia: Revolutionary Test Shows Industry Leading Performance

 Hello Dear Readers, 

Today in this post, learn about PowerVia Test which is Intel's first to implement backside power in a product like chip, resulting in over 90% cell utilization and other gains. 



Intel is the first in the industry to implement backside power delivery on a product-like test chip, achieving the performance needed to propel the world into the next era of computing. PowerVia, which will be introduced on the Intel 20A process node in the first half of 2024, is Intel’s industry-leading backside power delivery solution. It solves the growing issue of interconnect bottlenecks in area scaling by moving power routing to the backside of a wafer.

PowerVia is a major milestone in our aggressive ‘five nodes in four years’ strategy and on our path to achieving a trillion transistors in a package in 2030. Using a trial process node and subsequent test chip-enabled us to de-risk backside power for our leading process nodes, placing Intel a node ahead of competitors in bringing backside power delivery to market.

How It Works:

Intel decoupled the development of PowerVia from transistor development to ensure its readiness for silicon implementation based on Intel 20A and Intel 18A process nodes. PowerVia was tested on its own internal test node to debug and ensure good functionality of the technology before its integration with RibbonFET in Intel 20A. After fabrication and testing on a silicon test chip, PowerVia was confirmed to bring a remarkably efficient use of chip resources with greater than 90% cell utilization and major transistor scaling, enabling chip designers to achieve performance and efficiency gains in their products.

Why It Matters:

PowerVia is well ahead of competitors’ backside power solutions, giving chip designers – including Intel Foundry Services (IFS) customers – a faster path to valuable energy and performance gains in their products. Intel has a long track record of introducing the industry’s most critical new technologies, such as strained silicon, Hi-K metal gate, and FinFET, to propel Moore’s Law forward. With PowerVia and RibbonFET gate-all-around technology coming in 2024, Intel continues to lead the industry in chip design and process innovations.   

PowerVia is the first to solve the growing interconnect bottleneck issue for chip designers. Surging use cases, including artificial intelligence and graphics, require smaller, denser, and more powerful transistors to meet ever-growing computing demands. Today and for the past many decades, power and signal lines within a transistor’s architecture have competed for the same resources. By separating the two, chips can increase performance and energy efficiency, and deliver better results for customers. Backside power delivery is vital to transistor scaling, enabling chip designers to increase transistor density without sacrificing resources to deliver more power and performance than ever. 



How They Are Doing It: 

Intel 20A and Intel 18A will introduce both PowerVia backside power technology and RibbonFET gate-all-around technology. As a completely new way of delivering power to the transistors, backside power implementation raised new challenges for thermals and debugging designs.  

By decoupling the development of PowerVia from RibbonFET, Intel could work through those challenges quickly to ensure readiness for implementation in silicon based on Intel’s 20A and 18A process nodes. Intel engineers developed mitigation techniques to prevent the thermals from becoming an issue. The debug community also developed new techniques to ensure the new design structure could be appropriately de-bugged. As a result, the test implementation delivered solid yield and reliability metrics while demonstrating the intrinsic value proposition of the technology well before it joins the new RibbonFET architecture. 

The test also leveraged design rules enabled by EUV (extreme ultraviolet) lithography, which produced results including standard cell utilization of more than 90% over large areas of the die, enabling greater cell density, which can be expected to lower costs. The test also showed more than 30% platform voltage droop improvement and a 6% frequency benefit. Intel also achieved thermal characteristics in the PowerVia test chip in line with higher power densities expected from logic scaling. 


Importance of 3DIC Ecosystem in the VLSI Market


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