Skip to main content

Senior Eng CAD Engineering at Global Foundries

Hello Dear Readers,   Currently at Global Foundries, vacancy for Senior Eng CAD Engineering role. About GlobalFoundries: GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com. Introduction: Technology Computer Aided Design tools are critical to accelerate the technology development and deployment in our Fabs. We are seeking to strengthen our TCAD team with highly motivated Individuals who are at the early phase of their career. The candidate brings passion for semiconductor technologies and devices, strives for high-quality work, cares about details, and is willing to learn and cooperate in a...

Hardware RTL DV Engineer at HARMAN International

 Hello Dear Readers,

Currently at HARMAN International Bangalore vacancy for a Hardware RTL DV Engineer role.

As a technology leader that is rapidly on the move, HARMAN is filled with people who are focused on making life better. Innovation, inclusivity, and teamwork are a part of our DNA. When you add that to the challenges we take on and solve together, you’ll discover that at HARMAN you can grow, make a difference and be proud of the work you do every day.

Mandatory Skills:

  • You work closely with engineers across performance modeling, validation, and implementation to meet all functional requirements, performance, power and area goals
  • Leading, supervising, coaching, and mentoring a small team of RTL & DV engineers
  • Micro-architecture of digital blocks and hardware/firmware partitioning
  • Digital design and RTL coding, scripting, and automation
  • Conducting and subjecting to documentation and code reviews
  • Contributing to test plans and calling out design and verification requirements for tracking
  • Creating Engineering Change Requests (ECRs) and implementing and verifying Engineering Change Orders (ECOs) on RTL, and on synthesized, pre- and post-route netlists
  • Coordinating with leads from other teams such as DFT, analog design, protocol-specific PCS design, I/O controller teams, microcontroller firmware, IP/SOC deployment, front-end design, physical design, post-silicon validation
  • Interfacing with internal and external development partners, IP vendors, and service providers
  • System Verilog, UVM, Test bench Creation.

Preferred:

  • Any Scripting Language Knowledge
  • Good Leadership and Solutioning skillsets.

Comments

  1. Wonderful opportunity. Thanks for posting.

    ReplyDelete
  2. Thanks brother I have shortlisted for this position your resume building tips was helpful.

    ReplyDelete

Post a Comment

Popular posts from this blog

Exploring the Role of LEF Files in VLSI Chip Design: A Beginner's Guide

Hello Dear Readers,   Today in this post, I will provide some deep insight into the LEF file role during the VLSI Chip Design process. In VLSI (Very Large Scale Integration) design, a LEF file is a file that contains information about the physical geometry of the standard cells used in a circuit. LEF stands for Library Exchange Format. A standard cell is a pre-designed logic cell that contains a specific function, such as a flip-flop or an AND gate. Standard cells are designed to be easily combinable and scalable to create more complex circuits. The physical geometry of each standard cell is defined in the LEF file. The LEF file contains information such as the width, height, and position of the pins and metal layers of each standard cell. It also contains information about the physical design rules that govern the placement of these cells on the chip. LEF files are important in VLSI design because they enable the interoperability of different design tools from different vend...

Signal Electromigration (Signal EM): Violations, Examples, and Practical Fixes

  Hello Dear Readers,   Today in this post, I will provide some deep insight into the Signal Electromigration (Signal EM): Violations, Examples, and Practical Fixes. 1. Introduction: As technology nodes shrink into the deep‑submicron and nanometer regime (7nm, 5nm, 3nm and beyond), electromigration (EM) has become a first‑order reliability concern—not only for power/ground (PG) networks but also for signal nets. Signal EM failures are often underestimated because signal currents are transient and bidirectional. However, with higher switching activity, tighter metal pitches, thinner wires, and aggressive timing closure, signal EM can cause latent or early‑life failures if not addressed properly. This article explains: What Signal EM is and how it differs from PG EM Typical Signal EM violation scenarios Detailed, practical examples Root causes behind each violation Proven solutions and best practices to fix and prevent Signal EM issues 2. What is Signal Electromigration: El...

Physical Design/PDK methodology Engineer

Hello Dear Readers, At Applied Materials Bangalore, there is a vacancy for a Physical Design/PDK methodology Engineer role. Applied Materials is a global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service cutting-edge equipment that helps our customers manufacture display and semiconductor chips – the brains of devices we use every day. As the foundation of the global electronics industry, Applied enables the exciting technologies that literally connect our world – like AI and IoT. If you want to push the boundaries of materials science and engineering to create next generation technology, join us to deliver material innovation that changes the world.  Key Responsibility: Expertise in PDK enablement and library  validation/automation. Hands-on experience with LVS/Parasitic extraction/standard cell characterization flows and methodologies Design/System level experience with DTCO and ...