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Physical Design Methodology Engineer at Texas Instruments

  Hello Dear Readers, Texas Instruments Bangalore has a vacancy for the Physical Design Engineer role. We need an Physical Design Methodology Engineer to join our ATD team. The candidate should have a strong background in back-end design of ASIC/SoC chips. The ideal candidate will have a bachelor’s or master’s degree in Electrical Engineering or a related field. Requirements: 1 - 2 Years of experience in physical design Bachelor’s or master’s degree in Electrical/Electronics Engineering or a related field Strong understanding of physical design principles Must know the basics of floorplan, placement, CTS, routing, ECO, Physical Verification Proficiency in back-end design tools, such as Cadence Genus/Innovus/Tempus/Voltus Excellent problem-solving skills and attention to detail Effective communication and collaboration skills Responsibilities: Synthesis to GDSII Perform full Physical design flow and its verification Work closely with Digital Design and DFT engineers Ensure...
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Hardware RTL DV Engineer at HARMAN International

 Hello Dear Readers,

Currently at HARMAN International Bangalore vacancy for a Hardware RTL DV Engineer role.

As a technology leader that is rapidly on the move, HARMAN is filled with people who are focused on making life better. Innovation, inclusivity, and teamwork are a part of our DNA. When you add that to the challenges we take on and solve together, you’ll discover that at HARMAN you can grow, make a difference and be proud of the work you do every day.

Mandatory Skills:

  • You work closely with engineers across performance modeling, validation, and implementation to meet all functional requirements, performance, power and area goals
  • Leading, supervising, coaching, and mentoring a small team of RTL & DV engineers
  • Micro-architecture of digital blocks and hardware/firmware partitioning
  • Digital design and RTL coding, scripting, and automation
  • Conducting and subjecting to documentation and code reviews
  • Contributing to test plans and calling out design and verification requirements for tracking
  • Creating Engineering Change Requests (ECRs) and implementing and verifying Engineering Change Orders (ECOs) on RTL, and on synthesized, pre- and post-route netlists
  • Coordinating with leads from other teams such as DFT, analog design, protocol-specific PCS design, I/O controller teams, microcontroller firmware, IP/SOC deployment, front-end design, physical design, post-silicon validation
  • Interfacing with internal and external development partners, IP vendors, and service providers
  • System Verilog, UVM, Test bench Creation.

Preferred:

  • Any Scripting Language Knowledge
  • Good Leadership and Solutioning skillsets.

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Comments

  1. Anonymous2 December 2022 at 06:56

    Wonderful opportunity. Thanks for posting.

    ReplyDelete
  2. Anonymous5 December 2022 at 03:42

    Thanks brother I have shortlisted for this position your resume building tips was helpful.

    ReplyDelete
  3. Anonymous11 December 2022 at 12:21

    Still hiring??

    ReplyDelete

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