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VLSI Packaging Evolution and Innovations

Hello Dear Readers,   Today in this post, I will provide some deep insight into the VLSI packaging evolution and innovations. Semiconductor packaging has evolved from a simple protective housing into a critical performance enabler. In the modern VLSI landscape, packaging is no longer an afterthought; it is a fundamental determinant of PPA (Power, Performance, and Area) metrics, often dictating the thermal limits and signal integrity of the final SoC. 1. Traditional Packaging Technologies: These methods are the workhorses of the industry, widely used for low-to-medium complexity devices where cost-efficiency is paramount. Wire Bonding (QFN, QFP, DIP): Wire bonding is the most mature interconnection technology. It uses thin gold, copper, or aluminum wires to connect the die's bond pads to the package's internal leadframe. Implementation: The die is attached face-up to a leadframe or substrate. A wire bonder uses thermocompression or ultrasonic energy to attach wires betwee...
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Hardware RTL DV Engineer at HARMAN International

 Hello Dear Readers,

Currently at HARMAN International Bangalore vacancy for a Hardware RTL DV Engineer role.

As a technology leader that is rapidly on the move, HARMAN is filled with people who are focused on making life better. Innovation, inclusivity, and teamwork are a part of our DNA. When you add that to the challenges we take on and solve together, you’ll discover that at HARMAN you can grow, make a difference and be proud of the work you do every day.

Mandatory Skills:

  • You work closely with engineers across performance modeling, validation, and implementation to meet all functional requirements, performance, power and area goals
  • Leading, supervising, coaching, and mentoring a small team of RTL & DV engineers
  • Micro-architecture of digital blocks and hardware/firmware partitioning
  • Digital design and RTL coding, scripting, and automation
  • Conducting and subjecting to documentation and code reviews
  • Contributing to test plans and calling out design and verification requirements for tracking
  • Creating Engineering Change Requests (ECRs) and implementing and verifying Engineering Change Orders (ECOs) on RTL, and on synthesized, pre- and post-route netlists
  • Coordinating with leads from other teams such as DFT, analog design, protocol-specific PCS design, I/O controller teams, microcontroller firmware, IP/SOC deployment, front-end design, physical design, post-silicon validation
  • Interfacing with internal and external development partners, IP vendors, and service providers
  • System Verilog, UVM, Test bench Creation.

Preferred:

  • Any Scripting Language Knowledge
  • Good Leadership and Solutioning skillsets.

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Comments

  1. Anonymous2 December 2022 at 06:56

    Wonderful opportunity. Thanks for posting.

    ReplyDelete
  2. Anonymous5 December 2022 at 03:42

    Thanks brother I have shortlisted for this position your resume building tips was helpful.

    ReplyDelete
  3. Anonymous11 December 2022 at 12:21

    Still hiring??

    ReplyDelete

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