Design of the Single Cycle Microprocessor Using Verilog HDL

Hello Dear Readers,

Here I have uploaded my designed single cycle 8-bit CISC microprocessor using Verilog HDL. So Let's see and try your own as per your specification.

First of all, as we know CISC microprocessor has separate instruction memory and data memory so here I have make two text file for that and then designed one by one block of the microprocessor such as clock generation, ALU(Arithmetic Logical Unit), File reading as well as writing back, ...etc.

Verilog Code:

module microprocessor1();

reg reset;

reg clock;

reg [7:0] Dmem[0:255];// data memory array for the data file stored

reg [31:0] Imem[0:255];// instruction memory array for the instruction stored

reg [7:0] pc; // 8-bit program counter

reg [31:0] instruction; // 32-bit Instruction Register

reg [7:0] opcode; // 8-bit opcode

reg [7:0] destAddr; // 8-bit Destination Address

reg [7:0] src1Addr; // 8-bit Source Address #1

reg [7:0] src2Addr; // 8-bit Source Address #2

reg [7:0] src1Data; // 8-bit Source Data #1

reg [7:0] src2Data; // 8-bit Source Data #2

reg [7:0] Result; // 8-bit Result Data

reg [7:0] braAddr; // 8-bit Relative Branch address

integer outfile1;

integer i;

// define mnemonics of the designed microprocessor

//`define ADD 8'b00000000

//`define SUB 8'b00000001

//`define MUL 8'b00000010

//`define DIV 8'b00000011

//`define BRA 8'b00000100

integer clock_period=50;

/****************************************************************************

clcok generation block

*****************************************************************************/

initial

begin

clock=1'b0;

reset=1'b0;

end

always

#(clock_period/2) clock=~clock;

always

#10000 reset=~reset;

/*******************************************************************************

Designing of the Microprocessor Model

*******************************************************************************/

always @(posedge clock or posedge reset) begin

if(reset)

begin // Reset Sequence is genereted here for disable opreration aswell as reset program counter

disable fetch_and_execute;

pc=0;

end

else begin : fetch_and_execute // Fetch and execute instructions

instruction=Imem[pc];

// we divided the instruction register for the performing operation according to the instruction which is given

opcode=instruction[31:24]; // Get Opcode

destAddr=instruction[23:16]; // Get Destination Data Address

src1Addr=instruction[15:8]; // Get Source Data Address #1

src2Addr=instruction[7:0]; // Get Source Data Address #2

braAddr=instruction[23:16]; // Get relative address for BRA instruction

case(opcode)

//`ADD:

8'b00000000:

begin

$display("ADD INSTRUCTION:");

src1Data=Dmem[src1Addr]; // Get Data Operands

src2Data=Dmem[src2Addr];

Result=src1Data+src2Data; // Calculate Result

Dmem[destAddr]=Result; // Write Result data

#(clock_period) pc=pc+1; // ADD instruction takes one clock cycle

end

//`SUB:

8'b00000001:

begin

$display("SUB INSTRUCTION:");

src1Data=Dmem[src1Addr]; // Get Data Operands

src2Data=Dmem[src2Addr];

Result=src1Data-src2Data; // Calculate Result

Dmem[destAddr]=Result; // Write Result data

#(clock_period) pc=pc+1; // SUB instruction takes one clock cycle

end

//`MUL:

8'b00000010:

begin

$display("MUL INSTRUCTION:");

src1Data=Dmem[src1Addr]; // Get Data Operands

src2Data=Dmem [src2Addr];

Result=src1Data*src2Data; // Calculate Result

Dmem[destAddr]=Result; // Write Result Data

// MUL instruction takes three clock cycles

#(3*clock_period) pc=pc+1;

end

//DIV:

8'b00000011:

begin

$display("DIV INSTRUCTION:");

src1Data=Dmem[src1Addr];

src2Data=Dmem[src2Addr];

Result=src1Data/src2Data;

Dmem[destAddr]=Result;

// DIV instruction takes three clock cycles

#(3*clock_period) pc=pc+1; // increment program counter

end

//`BRA:

8'b00000100:

begin

$display("BRA INSTRUCTION:");

// BRA instruction takes two clock cycles

#(2*clock_period) pc=pc+braAddr; // calculate new program counter

end

endcase

end

/****************************************************************************

Display the updation of the status of the microprocessor

****************************************************************************/

initial

begin

// Display a header for the test Output

$display("\t PROG DEST SRC1 SRC2 SRC1 SRC2 RESULT");

$display("\t TIME RESET CNTR OPCODE ADDR ADDR ADDR DATA DATA DATA");

$display("\t---- ---- ---- ------ ---- ---- ---- ---- ------\n");

// Display Results at every clock edge

forever @(posedge clock)

$display ("\t %0d \t %b %h %h %h %h %h %h %h %h",

$time,reset,pc,opcode,destAddr,src1Addr,src2Addr,src1Data,src2Data, Result);

end

/******************************************************************************

Initialized and the sun after writing the assembly level data and the instruction text file

******************************************************************************/

initial

begin

$readmemh("instruction.txt",Imem); // Initialize instruction memory

$readmemh("data.txt",Dmem); // Initialize data memory

#(256*clock_period);

outfile1=$fopen("data.txt","w");

for (i = 0; i<256; i=i+1) begin

$fwrite(outfile1,"%d\n",Dmem[i]); //write as decimal in the data memory file after performed operation as per code

end

$fclose(outfile1);

end

endmodule

Simulational Results:

Here I wrote instruction hex code in the text file that will be fetching and decoding and corresponding data will be taken from the data memory and store back the results.