Dear Readers,   Today, we will be talking about STA, which is commonly referred to as static timing analysis. What is the actual meaning of it? What is the reason for doing it? What is the role of STA engineers in the real world? Many of us know that physical design is vast, and placing macros and standard cells interconnected with some metal layers is not enough. It's important to ensure that the input data gets to the output on time without any corruption or overwriting. For that, we need to do Setup and hold checks. What are these setup and hold? What are the reasons behind these timing violations? What is crosstalk, noise, timing arc, and unateness? What are the signoff checks we (STA engineers) do before the chip is going to tape out? All of these concepts we will discuss under this STA topic one by one in detail. Please stay tuned. Continue to read and learn with us. It's going to be fun😇 What is static timing analysis (STA)? Timing analysis is the evaluation of a design...

  Hello Dear Readers, Currently, at Si14 Semiconductor Pvt. Ltd has a  vacancy for a Physical Verification Engineer role. Job Title: Physical Verification Engineer Job Overview: As a Physical Verification Engineer, you will be responsible for validating and ensuring the physical correctness of integrated circuit layouts. This role involves working closely with the design and manufacturing teams to identify and resolve issues related to layout design, design rule violations, and overall chip manufacturability. Key Responsibilities: Layout Verification: Perform physical verification checks to ensure compliance with design rules and specifications. Identify and resolve layout-related issues, including DRC (Design Rule Check), LVS (Layout versus Schematic), and ERC (Electrical Rule Check) violations. Collaboration: Work closely with the IC design team to understand the design intent and constraints. Collaborate with other verification teams, such as DFT (Design for Test)...

  Hello Dear Readers,   Today in this post, learn about PowerVia Test which is Intel's first to implement backside power in a product like chip, resulting in over 90% cell utilization and other gains.  Intel is the first in the industry to implement backside power delivery on a product-like test chip, achieving the performance needed to propel the world into the next era of computing. PowerVia, which will be introduced on the Intel 20A process node in the first half of 2024, is Intel’s industry-leading backside power delivery solution. It solves the growing issue of interconnect bottlenecks in area scaling by moving power routing to the backside of a wafer. PowerVia is a major milestone in our aggressive ‘five nodes in four years’ strategy and on our path to achieving a trillion transistors in a package in 2030. Using a trial process node and subsequent test chip-enabled us to de-risk backside power for our leading process nodes, placing Intel a node ahead of competi...

Hello Dear Readers, Currently, at Exiger Technologies Bangalore vacancy for the VLSI ASIC library design Engineer Trainee role. Job description: We are looking for B Tech/M Tech EC/EE graduates from the year 2022 batch to be trained as Std cell/Memory design/AMS verification and characterization engineers. The selected candidates will undergo intense training in the above areas and will have opportunities to work in Advanced Technology Nodes. Please note that we are not considering 2023 graduates for these roles. Requirements: Should have consistently scored above 70% in the academic programs Candidates should have preferably done projects or trained in the VLSI domain such as Analog Design/Digital Design/Physical design Good in CMOS-based design, circuit analysis Apply Here Connect with me  1.Linkedln 2.Instagram 3.Facebook 4.WhatsApp