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Physical Design Methodology Engineer at Texas Instruments

  Hello Dear Readers, Texas Instruments Bangalore has a vacancy for the Physical Design Engineer role. We need an Physical Design Methodology Engineer to join our ATD team. The candidate should have a strong background in back-end design of ASIC/SoC chips. The ideal candidate will have a bachelor’s or master’s degree in Electrical Engineering or a related field. Requirements: 1 - 2 Years of experience in physical design Bachelor’s or master’s degree in Electrical/Electronics Engineering or a related field Strong understanding of physical design principles Must know the basics of floorplan, placement, CTS, routing, ECO, Physical Verification Proficiency in back-end design tools, such as Cadence Genus/Innovus/Tempus/Voltus Excellent problem-solving skills and attention to detail Effective communication and collaboration skills Responsibilities: Synthesis to GDSII Perform full Physical design flow and its verification Work closely with Digital Design and DFT engineers Ensure...
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Physical Verification Engineer at Si14 Semiconductor Pvt. Ltd

 Hello Dear Readers,

Currently, at Si14 Semiconductor Pvt. Ltd has a vacancy for a Physical Verification Engineer role.

Job Title: Physical Verification Engineer


Job Overview:

As a Physical Verification Engineer, you will be responsible for validating and ensuring the physical correctness of integrated circuit layouts. This role involves working closely with the design and manufacturing teams to identify and resolve issues related to layout design, design rule violations, and overall chip manufacturability.

Key Responsibilities:

  • Layout Verification:
  • Perform physical verification checks to ensure compliance with design rules and specifications.
  • Identify and resolve layout-related issues, including DRC (Design Rule Check), LVS (Layout versus Schematic), and ERC (Electrical Rule Check) violations.
  • Collaboration:
  • Work closely with the IC design team to understand the design intent and constraints.
  • Collaborate with other verification teams, such as DFT (Design for Test) and STA (Static Timing Analysis), to address cross-functional issues.
  • Tool Expertise:
  • Utilize industry-standard EDA (Electronic Design Automation) tools for physical verification.
  • Stay updated on the latest tools and methodologies in physical verification.
  • Documentation:
  • Create and maintain documentation related to physical verification procedures, methodologies, and results.
  • Provide regular updates to project teams on physical verification progress.
  • Troubleshooting:
  • Investigate and troubleshoot layout issues, working closely with design and layout engineers to implement effective solutions.
  • Develop and implement strategies to improve layout efficiency and manufacturability.
  • Process Improvement:
  • Contribute to the development and improvement of physical verification methodologies and best practices.
  • Participate in post-layout analysis and feedback to enhance future design processes.

Qualifications:

  • Bachelor's/Master's/Ph.D. in Electrical Engineering, Computer Engineering, or a related field.
  • Strong understanding of semiconductor device physics and IC design principles.
  • Proficiency in using EDA tools for physical verification (Calibre, IC Validator, etc.).
  • Familiarity with scripting languages (e.g., Python, Perl) for automation of verification tasks.
  • Excellent problem-solving skills and attention to detail.
  • Effective communication and collaboration skills for working in cross-functional teams.

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