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Verification Engineer or Senior Verification Engineer SOC at MIPS India

Hello Dear Readers, Currently, at MIPS India  vacancy for a Verification Engineer or Senior Verification Engineer SOC role. We are seeking an experienced Verification Engineer or Senior Verification Engineer SOC. This position involves extensive hands-on experience with CPU verification using industry-standard functional verification methodologies, formal verification, and constrained random generators, and reference model-based checkers. The candidate must be able to take critical decisions and completely own verification closure for a block or feature. This position involves cross-functional interaction with CPU designers and architects and working across sites to ensure high-quality CPU designs for customers. You will: Take full ownership and drive verification efforts to closure Work closely with designers and architects to understand specifications at unit/top level Understand use cases and develop functional test plans Develop directed tests written in C, Assembly, and SystemVeri
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Physical Verification Engineer at Si14 Semiconductor Pvt. Ltd

 Hello Dear Readers,

Currently, at Si14 Semiconductor Pvt. Ltd has a vacancy for a Physical Verification Engineer role.

Job Title: Physical Verification Engineer


Job Overview:

As a Physical Verification Engineer, you will be responsible for validating and ensuring the physical correctness of integrated circuit layouts. This role involves working closely with the design and manufacturing teams to identify and resolve issues related to layout design, design rule violations, and overall chip manufacturability.

Key Responsibilities:

  • Layout Verification:
  • Perform physical verification checks to ensure compliance with design rules and specifications.
  • Identify and resolve layout-related issues, including DRC (Design Rule Check), LVS (Layout versus Schematic), and ERC (Electrical Rule Check) violations.
  • Collaboration:
  • Work closely with the IC design team to understand the design intent and constraints.
  • Collaborate with other verification teams, such as DFT (Design for Test) and STA (Static Timing Analysis), to address cross-functional issues.
  • Tool Expertise:
  • Utilize industry-standard EDA (Electronic Design Automation) tools for physical verification.
  • Stay updated on the latest tools and methodologies in physical verification.
  • Documentation:
  • Create and maintain documentation related to physical verification procedures, methodologies, and results.
  • Provide regular updates to project teams on physical verification progress.
  • Troubleshooting:
  • Investigate and troubleshoot layout issues, working closely with design and layout engineers to implement effective solutions.
  • Develop and implement strategies to improve layout efficiency and manufacturability.
  • Process Improvement:
  • Contribute to the development and improvement of physical verification methodologies and best practices.
  • Participate in post-layout analysis and feedback to enhance future design processes.

Qualifications:

  • Bachelor's/Master's/Ph.D. in Electrical Engineering, Computer Engineering, or a related field.
  • Strong understanding of semiconductor device physics and IC design principles.
  • Proficiency in using EDA tools for physical verification (Calibre, IC Validator, etc.).
  • Familiarity with scripting languages (e.g., Python, Perl) for automation of verification tasks.
  • Excellent problem-solving skills and attention to detail.
  • Effective communication and collaboration skills for working in cross-functional teams.

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