Skip to main content

SoC RTL Design Engineer at Texas Instruments

  Hello Dear Readers, At Texas Instruments Bangalore, there is a vacancy for SoC RTL Design Engineer role. Are you looking for a career at one of the leading semiconductor companies in the world Texas Instruments (TI) is looking for a SoC RTL Design Engineer to join the team of enthusiastic engineers who develops highly complex mixed signal devices for audio applications with industry leading performance. These audio products are truly mixed-signal devices with highly integrated digital circuits such as a DSP core for digital filters and audio signal processing blocks, hardware processing blocks, analog controllers, various serial interfaces (Audio serial interfaces, I2C, SPI) and other digital blocks like clock-generation, registers map, Interrupts etc. This is a great opportunity to be part of an established team that’s continuing to look for growth opportunities, working with worldwide leading customers and developing cutting edge solutions in the areas of consumer electr...
Post a Comment

Physical Verification Engineer at Si14 Semiconductor Pvt. Ltd

 Hello Dear Readers,

Currently, at Si14 Semiconductor Pvt. Ltd has a vacancy for a Physical Verification Engineer role.

Job Title: Physical Verification Engineer


Job Overview:

As a Physical Verification Engineer, you will be responsible for validating and ensuring the physical correctness of integrated circuit layouts. This role involves working closely with the design and manufacturing teams to identify and resolve issues related to layout design, design rule violations, and overall chip manufacturability.

Key Responsibilities:

  • Layout Verification:
  • Perform physical verification checks to ensure compliance with design rules and specifications.
  • Identify and resolve layout-related issues, including DRC (Design Rule Check), LVS (Layout versus Schematic), and ERC (Electrical Rule Check) violations.
  • Collaboration:
  • Work closely with the IC design team to understand the design intent and constraints.
  • Collaborate with other verification teams, such as DFT (Design for Test) and STA (Static Timing Analysis), to address cross-functional issues.
  • Tool Expertise:
  • Utilize industry-standard EDA (Electronic Design Automation) tools for physical verification.
  • Stay updated on the latest tools and methodologies in physical verification.
  • Documentation:
  • Create and maintain documentation related to physical verification procedures, methodologies, and results.
  • Provide regular updates to project teams on physical verification progress.
  • Troubleshooting:
  • Investigate and troubleshoot layout issues, working closely with design and layout engineers to implement effective solutions.
  • Develop and implement strategies to improve layout efficiency and manufacturability.
  • Process Improvement:
  • Contribute to the development and improvement of physical verification methodologies and best practices.
  • Participate in post-layout analysis and feedback to enhance future design processes.

Qualifications:

  • Bachelor's/Master's/Ph.D. in Electrical Engineering, Computer Engineering, or a related field.
  • Strong understanding of semiconductor device physics and IC design principles.
  • Proficiency in using EDA tools for physical verification (Calibre, IC Validator, etc.).
  • Familiarity with scripting languages (e.g., Python, Perl) for automation of verification tasks.
  • Excellent problem-solving skills and attention to detail.
  • Effective communication and collaboration skills for working in cross-functional teams.

Comments

Post a Comment

Popular posts from this blog

Internship - SoC /IP Design at NXP India

Hello Dear Readers, Currently, at NXP India  vacancy for  Internship - SoC /IP Design   role.   We are looking for a Master degree student with Electronics and Communication Engineering, or related field, with an emphasis on SoC design. This is a full-time internship with a duration of about 11-12 months. Job Responsibility: Working with our experienced design team to design state of the art SoC hardware specific segment applications like Automotive, IoT, voice/object recognition, security, smart connectivity and touch sensing . Assisting experienced engineers with End-to-end ownership of SoC Design, Verification and implementation (Physical Design). Design and verify digital and Mixed-signal IPs. Document designs and present results. Job Qualification: Master student in electronic/computer engineering Creative and positive mindset Good knowledge on CMOS technologies Great communication skills, interpersonal skills, teamwork skills and can-do attitude Desire for a ca...
Post a Comment
Read more

Best Book for Designing Microarchitecture of Microprocessor Using Verilog HDL

  Hello Dear Readers, Currently, after succeeding in many topics now I starting to provide technical book reviews which were I have completed and still read books always. So let us start today's book review. Book Name:   Computer Principles and Design in Verilog  HDL Description:  Uses Verilog HDL to illustrate computer architecture and microprocessor design, allowing readers to readily simulate and adjust the operation of each design, and thus build industrially relevant skills Introduces the computer principles, computer design, and how to use Verilog HDL (Hardware Description Language) to implement the design Provides the skills for designing processor/arithmetic/cpu chips, including the unique application of Verilog HDL material for CPU (central processing unit) implementation Despite the many books on Verilog and computer architecture and microprocessor design, few, if any, use Verilog as a key tool in helping a student to understand these design techniques...
3 comments
Read more

Exploring the Role of LEF Files in VLSI Chip Design: A Beginner's Guide

Hello Dear Readers,   Today in this post, I will provide some deep insight into the LEF file role during the VLSI Chip Design process. In VLSI (Very Large Scale Integration) design, a LEF file is a file that contains information about the physical geometry of the standard cells used in a circuit. LEF stands for Library Exchange Format. A standard cell is a pre-designed logic cell that contains a specific function, such as a flip-flop or an AND gate. Standard cells are designed to be easily combinable and scalable to create more complex circuits. The physical geometry of each standard cell is defined in the LEF file. The LEF file contains information such as the width, height, and position of the pins and metal layers of each standard cell. It also contains information about the physical design rules that govern the placement of these cells on the chip. LEF files are important in VLSI design because they enable the interoperability of different design tools from different vend...
4 comments
Read more