Hello Dear Readers,   Today in this post, I will provide some deep insight into the LEF file role during the VLSI Chip Design process. In VLSI (Very Large Scale Integration) design, a LEF file is a file that contains information about the physical geometry of the standard cells used in a circuit. LEF stands for Library Exchange Format. A standard cell is a pre-designed logic cell that contains a specific function, such as a flip-flop or an AND gate. Standard cells are designed to be easily combinable and scalable to create more complex circuits. The physical geometry of each standard cell is defined in the LEF file. The LEF file contains information such as the width, height, and position of the pins and metal layers of each standard cell. It also contains information about the physical design rules that govern the placement of these cells on the chip. LEF files are important in VLSI design because they enable the interoperability of different design tools from different vendors.

  Hello Dear Readers,   Today in this series of posts, I will provide some deep insight into the RISC-V microprocessor and its Implementation using Verilog HDL. RISC-V is an open-source instruction set architecture (ISA) designed for modern computer processors. It is a relatively new ISA that has gained popularity recently due to its flexibility, simplicity, and open-source nature. The name "RISC-V" stands for Reduced Instruction Set Computing - Five, which refers to the fact that it is based on a simple, streamlined set of instructions. One of the key features of RISC-V is its modular design, which allows for customization and scalability. This means that designers can choose which instructions to include and how to implement them, which can result in more efficient and specialized processors. Additionally, because RISC-V is open-source, it is free to use and can be modified by anyone, making it a popular choice for academic research and experimentation. RISC-V also incl

  Hello Dear Readers,   Currently at Global Foundries vacancy for an Intern - Design & Technology Enablement role. GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. Introduction: As part of the PDK infrastructure group, the candidate will contribute to the software development of Process Design Kits and Design Manual infrastructure efficiency and innovation projects. Your Job : Contribute to the development and testing of PDK infrastructure group Propose and develop software-based solutions for technical needs Communicate with the team to understand the requirements and report status Other Responsibilities:  Perform all activities

Hello Dear Readers, Currently, at Wafer Space Bangalore vacancy for an RTL Front End Design Engineers role. Job Responsibilities: Chip integration of high complexity SOCs. Coordinating with various IP owners on receivables and DV, synthesis and Emulation for deliverables Spyglass/CDC for the full chip and will evaluate the incoming bugs and take appropriate action Formal Verification between RTL to Netlist and Netlist to Netlist Manual and Conformal ECO Running Lint (Spyglass) at SoC level. Chip-level integration and connectivity. Debugging FV failures ECO implementation. Desired Skills and Experience: 2 - 10 years of experience Sound knowledge in Micro Architecture design and RTL implementation Understanding of ARM SoCs with AXI/AHB buses, peripherals, CPUs, and mobile SOCs is desirable Experience in Synthesis and pre-layout timing analysis Understanding of DFT flow is desirable Experiencing using clear case a must Experienced with VHDL/Verilog/coding and tools like VCS/Verdi/Spyglass