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VLSI Packaging Evolution and Innovations

Hello Dear Readers,   Today in this post, I will provide some deep insight into the VLSI packaging evolution and innovations. Semiconductor packaging has evolved from a simple protective housing into a critical performance enabler. In the modern VLSI landscape, packaging is no longer an afterthought; it is a fundamental determinant of PPA (Power, Performance, and Area) metrics, often dictating the thermal limits and signal integrity of the final SoC. 1. Traditional Packaging Technologies: These methods are the workhorses of the industry, widely used for low-to-medium complexity devices where cost-efficiency is paramount. Wire Bonding (QFN, QFP, DIP): Wire bonding is the most mature interconnection technology. It uses thin gold, copper, or aluminum wires to connect the die's bond pads to the package's internal leadframe. Implementation: The die is attached face-up to a leadframe or substrate. A wire bonder uses thermocompression or ultrasonic energy to attach wires betwee...
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Intern - CAD Automation at Global Foundries

  Hello Dear Readers,   Currently at Global Foundries vacancy for an Intern - CAD Automation role. GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. Introduction: This position is for a CAD flow/ EDA Engineer who will work on EDA/CAD related topics. The successful candidate needs to have a good background in working on CAD/EDA infrastructure and needs to be a team player with a solution-oriented approach. Your Job:    Work on CAD design environment, PDK versioning and enablement and Tool license management related topics. Digital design background with Skill/python, scripting, logic verification and porting...
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Introduction to Low Power in the VLSI Chip Design and Techniques for Switching and Leakage Power Reduction

  Hello Dear Readers,   Today in this series of posts I will provide some deep insight into low-power VLSI design flow and the different techniques to reduce different components of power consumption. It’s no secret that power is emerging as the most critical issue in system-on-chip (SoC) design today. Power management is becoming an increasingly urgent problem for almost every category of design, as power density—measured in watts per square millimeter—rises at an alarming rate. From a chip-engineering perspective, effective energy management for an SoC must be built into the design starting at the architecture stage; and low-power techniques need to be employed at every stage of the design, from RTL to GDSII flow.  Fred Pollack of Intel first noted a rather alarming trend in his keynote at MICRO-32 in 1999. He made the now well-known observation that power density is increasing at an alarming rate, approaching that of the hottest man-made objects on the planet, an...
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The Importance of 3D IC Ecosystem Collaboration in the VLSI Market

  Hello Dear Readers,   Today in this post I will provide some deep insight into what is happening in the semiconductor industry. So I hope you like it and enjoy it to improve your knowledge and awareness about the industry.  So let's start it today we are discussing, The Importance of 3D IC Ecosystem Collaboration in the VLSI Market. As design teams continue to develop new generations of transformative products, the demand for computing remains relentless. Modern workloads have brought packaging technologies to the forefront for innovation and pushed the boundaries for silicon product design in terms of product performance, function and cost. Not too long ago, packaging technologies were thought of as inconvenient back-end processes. But times have changed, and rising advancements in artificial intelligence, big data, cloud computing, and autonomous vehicles have pushed the computing envelope unlike ever before (along with the need for packaging technologi...
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RTL - ASIC design and verification engineer at Cisco Bangalore

  Hello Dear Readers, Currently, Cisco Bangalore has a vacancy for RTL - ASIC design and verification engineer role. Cisco SiliconOne team is looking for a talented and a dynamic design verification engineer. You will have an ASIC background with hands-on experience in design verification, system testing, with in-depth knowledge of ASIC/SoC development cycle, the best industry practices, from specification through tape-out and lab validation, and a proven track record of success in high-performance/high-volume products. We are looking for motivated individuals, who have excellent analytical and problem solving abilities, who are open and have the ability to assimilate new techniques and enjoy challenging tasks. Who You Are: Proficient in Verilog Have extensive experience in ASIC front end design Strong experience with synthesis, timing analysis and power analysis Perl/Python/Makefile scripting is strongly preferred Experience designing ASICs for networking protocols (Ethernet,...
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