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Physical Design Methodology Engineer at Texas Instruments

  Hello Dear Readers, Texas Instruments Bangalore has a vacancy for the Physical Design Engineer role. We need an Physical Design Methodology Engineer to join our ATD team. The candidate should have a strong background in back-end design of ASIC/SoC chips. The ideal candidate will have a bachelor’s or master’s degree in Electrical Engineering or a related field. Requirements: 1 - 2 Years of experience in physical design Bachelor’s or master’s degree in Electrical/Electronics Engineering or a related field Strong understanding of physical design principles Must know the basics of floorplan, placement, CTS, routing, ECO, Physical Verification Proficiency in back-end design tools, such as Cadence Genus/Innovus/Tempus/Voltus Excellent problem-solving skills and attention to detail Effective communication and collaboration skills Responsibilities: Synthesis to GDSII Perform full Physical design flow and its verification Work closely with Digital Design and DFT engineers Ensure...
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RTL - ASIC design and verification engineer at Cisco Bangalore

 Hello Dear Readers,

Currently, Cisco Bangalore has a vacancy for RTL - ASIC design and verification engineer role.

Cisco SiliconOne team is looking for a talented and a dynamic design verification engineer. You will have an ASIC background with hands-on experience in design verification, system testing, with in-depth knowledge of ASIC/SoC development cycle, the best industry practices, from specification through tape-out and lab validation, and a proven track record of success in high-performance/high-volume products.

We are looking for motivated individuals, who have excellent analytical and problem solving abilities, who are open and have the ability to assimilate new techniques and enjoy challenging tasks.

Who You Are:

  • Proficient in Verilog
  • Have extensive experience in ASIC front end design
  • Strong experience with synthesis, timing analysis and power analysis
  • Perl/Python/Makefile scripting is strongly preferred
  • Experience designing ASICs for networking protocols (Ethernet, FC) a plus
  • Must be strong at documenting the design specifications, verification plan and presentations
  • Strong problem solving and ASIC debugging skills
  • Ability to debug system wide issues
  • MSEE or BSEE with 2+ years of related experience.

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