Hello Dear Readers, Today, I will explain how Finite State Machine (FSM) is modeling using Verilog HDL. The finite state machine (FSM) is a very important design block in the ASIC design. Most of the ASIC designs and controller design needs efficient and synthesizable state machines and are commonly called FSM. The FSMs can be described very efficiently by using the Verilog HDL and for ASIC design engineers. Basically, FSMs are predefined sequences on the preordered or defined events and are source synchronous designs. FSMs can be coded efficiently for the synthesizable outcome using the multiple- or single-procedural block. In the practical scenario, it is recommended to use the multiple-procedural blocks to describe the state machines. One of the procedural blocks can describe the combinational logic and level-sensitive to the inputs or the states. Whereas, the other procedural block can be edge sensitive to the positive edge of the clock or to the negative edge of the clock. 1). Sta

  Hello Dear Readers, Today, I will explain how functions and tasks are used in Verilog to make our lengthy code highly optimized. Task and functions are used in the Verilog to describe the commonly used functional behavior. Instead of replicating the same code at different places, it is good and common practice to use the functions or tasks depending on the requirement. For easy maintenance of the code, it is better to use the functions or tasks like the subroutine. Let's see the example below for a better understanding. 1). Counting 1’s from the Given String Using Functions: The following are the key important points that need to remember while using the function:  1. Function can not consists of the time control statements and even delay operators. 2. Function can have at least one input argument declaration.  3. Function can consist of function calls but function cannot consist of the task.  4. Function executes in zero simulation time and returns a single value when called. 

  Hello Dear Readers, Today, I will explain how to design a Layout in the MAGIC layout tool and how to perform SPICE simulation. CMOS inverters (Complementary NMOSFET Inverters) are some of the most widely used and adaptable MOSFET inverters used in chip design. They operate with very little power loss and at relatively high speed. Furthermore, the CMOS inverter has good logic buffer characteristics, in that, its noise margins in both low and high states are large. A CMOS inverter containing a PMOS and an NMOS transistor connected at the drain and gate terminals, a supply voltage VDD at the PMOS source terminal, and a ground connection at the NMOS source terminal Vin is connected to the gate terminals, and Vout is connected to the drain terminals As shown in Fig.1 is a circuit-level symbol but in the layout-wise internal structure of CMOS is consisted of common P-Type Substrate for building NMOS and N-Well implanted for building PMOS as shown in Fig.2.                        Fig.1 CMOS

  Hello Dear Readers, Today, I will explain what is ISA and how it is used to build digital computer systems. ISA is an important issue in hardware/software codesign. An ISA tells compiler developers “what a CPU can do,” and tells CPU designers “what a CPU should do.” Compiler developers use the ISA to develop compilers, and CPU designers design a CPU to implement the ISA. That is, an ISA is an interface between software and hardware, as shown in Fig.1. Fig.1 ISA as an interface between software and hardware An ISA defines the formats of instructions, the operations of instructions, the types of operands, the memory and registers the instructions can access, the byte order, and the addressing modes. Some popular ISAs include Intel’s x86, SGI/MIPS’s MIPS32/MIPS64, IBM’s PowerPC, SUN Microsystems’ SPARC, HP’s HP-PA, and ARM’s ARM. 1).  Instruction Types: An instruction type refers to what kind of operation is done by an instruction. The instruction types differ between ISAs. Some instru