What is Instruction Set Architecture (ISA) In Modern CPUs

Hello Dear Readers,

Today, I will explain what is ISA and how it is used to build digital computer systems.

ISA is an important issue in hardware/software codesign. An ISA tells compiler developers “what a CPU can do,” and tells CPU designers “what a CPU should do.” Compiler developers use the ISA to develop compilers, and CPU designers design a CPU to implement the ISA. That is, an ISA is an interface between software and hardware, as shown in Fig.1.

Fig.1 ISA as an interface between software and hardware

An ISA defines the formats of instructions, the operations of instructions, the types of operands, the memory and registers the instructions can access, the byte order, and the addressing modes. Some popular ISAs include Intel’s x86, SGI/MIPS’s MIPS32/MIPS64, IBM’s PowerPC, SUN Microsystems’ SPARC, HP’s HP-PA, and ARM’s ARM.

1). Instruction Types:

An instruction type refers to what kind of operation is done by an instruction. The instruction types differ between ISAs. Some instruction types that commonly appear in the modern ISAs are described below,

(i) Arithmetic Operation Type:

Instructions of this type perform arithmetic operations on integers, such as addition, subtraction, multiplication, division, and square root.

(ii) Logic Operation Type:

Logic operations include bitwise logical AND, OR, and NOT. Most ISAs provide NOR (NOT OR) or XOR (exclusive OR) instead of NOT.

(iii) Shift Operation Type:

There are mainly three types of shift instructions: logical shift left, logical shift right, and arithmetic shift right. Other shift instructions include arithmetic shift left, rotate shift, and rotate shift with carry.

(iv) Memory Access Type:

Memory access instructions transfer data between the memory and registers inside the CPU. A load instruction loads memory data to the register. A store instruction writes register data to the memory. All RISC (reduced instruction set computer) type ISAs have these two instructions but CISC (complex instruction set computer) type ISAs may combine them into computational instructions.

(v) Input/Output Access Type:

Input/output instructions transfer data between I/O and CPU registers. In most RISC type ISAs, some addresses of the virtual memory area are assigned to the I/O space so that the load and store instructions can be used to access I/O. This is called a memory-mapped I/O. CISC type ISAs may have a dedicated I/O space, therefore the input and output instructions must be prepared for accessing the I/O.

(vi) Control Transfer Type:

Control transfer instructions alter the order of the instruction execution. Conditional branch instructions confirm a condition to determine whether to branch to a target address. A jump instruction jumps to a target address unconditionally. A subroutine call instruction jumps to the entry of the subroutine and saves the return address to somewhere. And a return instruction returns from the subroutine.

(vii) Floating-Point Calculation Type:

All the computational instructions described above operate on integers. Floating-point instructions perform arithmetic operations on floating-point numbers. There are also some instructions that convert data formats between integers and floating-point numbers.

2). Instruction Architecture:

The instruction architectures decide how the CPU will store data. Fig.2 shows four instruction architectures that are used in modern CPUs. In a stack architecture, the operands are implicitly on top of the stack. Two source operands are popped from the top of the stack, and the result is pushed onto the stack. The stack has a feature of first-in last-out or last-in-first-out; it cannot be accessed randomly. JVM (Java virtual machine) Bytecode uses this architecture. In an accumulator architecture, one operand is implicitly in the accumulator and the other operand is in the memory or register. The operation result is stored in the accumulator implicitly. Z80 and 6502 ISAs use this architecture.

Fig.2 Instruction Architecture

In a register–memory architecture, one operand is explicitly in a general-purpose register file and the other operand is in the memory. The operation result is stored in the register. The Intel x86 ISA uses this architecture. In a register–register architecture, all operands are explicitly in a general-purpose register file. The operation result is also stored in the register. Almost all RISC-type ISAs use this architecture. The data transfer between the register file and memory is performed by load and store instructions.

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