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Physical Design/PDK methodology Engineer

Hello Dear Readers, At Applied Materials Bangalore, there is a vacancy for a Physical Design/PDK methodology Engineer role. Applied Materials is a global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service cutting-edge equipment that helps our customers manufacture display and semiconductor chips – the brains of devices we use every day. As the foundation of the global electronics industry, Applied enables the exciting technologies that literally connect our world – like AI and IoT. If you want to push the boundaries of materials science and engineering to create next generation technology, join us to deliver material innovation that changes the world.  Key Responsibility: Expertise in PDK enablement and library  validation/automation. Hands-on experience with LVS/Parasitic extraction/standard cell characterization flows and methodologies Design/System level experience with DTCO and ...
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Functions And Tasks In Verilog

 Hello Dear Readers,

Today, I will explain how functions and tasks are used in Verilog to make our lengthy code highly optimized.

Task and functions are used in the Verilog to describe the commonly used functional behavior. Instead of replicating the same code at different places, it is good and common practice to use the functions or tasks depending on the requirement. For easy maintenance of the code, it is better to use the functions or tasks like the subroutine. Let's see the example below for a better understanding.

1). Counting 1’s from the Given String Using Functions:

The following are the key important points that need to remember while using the function: 

1. Function can not consists of the time control statements and even delay operators.

2. Function can have at least one input argument declaration. 

3. Function can consist of function calls but function cannot consist of the task. 

4. Function executes in zero simulation time and returns a single value when called. 

5. It is not recommended to use the function while writing the synthesizable Verilog RTL. 

6. Functions are used for writing the behavioral or simulatable model. 

7. Functions should not have nonblocking assignments.

In this example, the function is used with the argument ‘‘data_in’’. The name of the function is ‘‘count_1s_in_byte’’. In most of the protocol descriptions, it is required to perform some operations on the input string. In this example, the string is an 8-bit input ‘‘data_in’’ and output result is 4-bit ‘‘out’’. Here code is parameterized so we can extend it to any number of bits of string. It is not recommended to use the function to generate synthesized logic.

Verilog Code:

module count_one #(parameter N=8)(data_in,out);

input [N-1:0] data_in;

output reg [N-5:0] out;

always @(data_in)

out=count_1s_in_string(data_in);


function [N-5:0] count_1s_in_string;

  input [N-1:0] data_in;

  integer i;

begin  

  count_1s_in_string=0;

 for(i=0;i<N;i=i+1)

  if(data_in[i]==1) count_1s_in_string=count_1s_in_string+1;

end

endfunction  

endmodule

2). Counting 1’s from the Given String Using Tasks:
The following are key important points that need to remember while using the task: 
1. Task can consist of the time control statements and even delay operators. 

2. Task can have input and output declarations. 

3. Task can consist of function calls but function cannot consist of the task. 

4. Task can have output argument and not be used to return the value when called. 

5. Task can be used to call other tasks. 

6. It is not recommended to use the task while writing the synthesizable Verilog RTL. 

7. Tasks are used for writing the behavioral or simulatable model.

Verilog Code:

module count_one #(parameter N=8)(data_in,out);

input [N-1:0] data_in;

output reg [N-5:0] out;

always @(data_in)

count_1s_in_string(data_in,out);


task count_1s_in_string;

  input [N-1:0] data_in;

  output reg [N-5:0] out;

  integer i;

begin  

  out=0;

 for(i=0;i<N;i=i+1)

  if(data_in[i]==1) out=out+1;

end

endtask  

endmodule

Simulational Results:





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Comments

  1. Anonymous3 September 2021 at 07:56

    Easy explanation

    ReplyDelete
  2. Anonymous3 September 2021 at 21:40

    Your site is last end point of our search. Keep it up

    ReplyDelete

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