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VLSI Packaging Evolution and Innovations

Hello Dear Readers,   Today in this post, I will provide some deep insight into the VLSI packaging evolution and innovations. Semiconductor packaging has evolved from a simple protective housing into a critical performance enabler. In the modern VLSI landscape, packaging is no longer an afterthought; it is a fundamental determinant of PPA (Power, Performance, and Area) metrics, often dictating the thermal limits and signal integrity of the final SoC. 1. Traditional Packaging Technologies: These methods are the workhorses of the industry, widely used for low-to-medium complexity devices where cost-efficiency is paramount. Wire Bonding (QFN, QFP, DIP): Wire bonding is the most mature interconnection technology. It uses thin gold, copper, or aluminum wires to connect the die's bond pads to the package's internal leadframe. Implementation: The die is attached face-up to a leadframe or substrate. A wire bonder uses thermocompression or ultrasonic energy to attach wires betwee...
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Physical Design Methodology Engineer at Texas Instruments

 Hello Dear Readers,

Texas Instruments Bangalore has a vacancy for the Physical Design Engineer role.

We need an Physical Design Methodology Engineer to join our ATD team. The candidate should have a strong background in back-end design of ASIC/SoC chips. The ideal candidate will have a bachelor’s or master’s degree in Electrical Engineering or a related field.


Requirements:

  • 1 - 2 Years of experience in physical design
  • Bachelor’s or master’s degree in Electrical/Electronics Engineering or a related field
  • Strong understanding of physical design principles
  • Must know the basics of floorplan, placement, CTS, routing, ECO, Physical Verification
  • Proficiency in back-end design tools, such as Cadence Genus/Innovus/Tempus/Voltus
  • Excellent problem-solving skills and attention to detail
  • Effective communication and collaboration skills

Responsibilities:

  • Synthesis to GDSII
  • Perform full Physical design flow and its verification
  • Work closely with Digital Design and DFT engineers
  • Ensure Design meets PPA targets
  • Develop as much automation as possible to debug and faster work



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