Hello Dear Readers, Currently at Dew Software Bangalore vacancy for Design Engineer - STA, SD, Power, PDN role. Dew Software, a leading player in the Digital Transformation space, is seeking a skilled Design Engineer specializing in STA (Static Timing Analysis), SD (Signal Integrity), Power, and PDN (Power Delivery Network) to join our team. Working with Fortune 500 companies to support their digital innovation and transformation strategies, the Design Engineer will be responsible for ensuring the integrity and efficiency of digital designs through comprehensive analysis and optimization. Dew Software is dedicated to delivering exceptional outcomes with cutting-edge technologies, and this is an excellent opportunity to contribute to the growth and success of our clients. Responsibilities: Perform STA (Static Timing Analysis) to ensure design meets timing requirements Conduct signal integrity analysis to optimize signal integrity and minimize signal integrity issues Provide power anal
Hello Dear Readers, Currently, Cisco Bangalore has a vacancy for RTL - ASIC design and verification engineer role. Cisco SiliconOne team is looking for a talented and a dynamic design verification engineer. You will have an ASIC background with hands-on experience in design verification, system testing, with in-depth knowledge of ASIC/SoC development cycle, the best industry practices, from specification through tape-out and lab validation, and a proven track record of success in high-performance/high-volume products. We are looking for motivated individuals, who have excellent analytical and problem solving abilities, who are open and have the ability to assimilate new techniques and enjoy challenging tasks. Who You Are: Proficient in Verilog Have extensive experience in ASIC front end design Strong experience with synthesis, timing analysis and power analysis Perl/Python/Makefile scripting is strongly preferred Experience designing ASICs for networking protocols (Ethernet, FC) a pl