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Physical Design Methodology Engineer at Texas Instruments

  Hello Dear Readers, Texas Instruments Bangalore has a vacancy for the Physical Design Engineer role. We need an Physical Design Methodology Engineer to join our ATD team. The candidate should have a strong background in back-end design of ASIC/SoC chips. The ideal candidate will have a bachelor’s or master’s degree in Electrical Engineering or a related field. Requirements: 1 - 2 Years of experience in physical design Bachelor’s or master’s degree in Electrical/Electronics Engineering or a related field Strong understanding of physical design principles Must know the basics of floorplan, placement, CTS, routing, ECO, Physical Verification Proficiency in back-end design tools, such as Cadence Genus/Innovus/Tempus/Voltus Excellent problem-solving skills and attention to detail Effective communication and collaboration skills Responsibilities: Synthesis to GDSII Perform full Physical design flow and its verification Work closely with Digital Design and DFT engineers Ensure...
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Physical Design Engineer at Texas Instruments

Hello Dear Readers,

At Texas Instruments Bangalore, there is a vacancy for the Physical Design Engineer role.

The Radar and Analytics group at Texas Instruments India is looking for passionate Physical Design Engineer to work on next-gen CMOS single-chip millimeter wave sensor portfolio for Automotive Radar and Industrial applications. Physical Design team here owns Complete SoC Synthesis to Layout closure including constraints development and STA & is responsible for design handoff to manufacturing. Physical Design team at Radar & Analytics also works closely with systems and designs team for PPA optimization and has good knowledge of system aspects of the device usage. 

Responsibilities:

  • As a Physical Design Engineer in the team, you will be working independently on the entire flow from RTL to GDSII.
  • Understand the design, clock architecture, reset architecture, DFT architecture and influence them as per Physical Design needs.
  • Responsible for Place & Route, Reliability and Physical verification, Reliability closure
  • Methodologies to keep the PD cycle efficient and predictable.
  • Techniques to reduce Power and Area to make the device competitive
  • Techniques used in automotive designs.
  • Ability to interface with Fab and Qualification teams.


Minimum Qualifications:

  • Bachelor or Master’s degree in Electrical/Electronics Engineering.
  • 1-2 years of Industry experience
  • Understanding of DFT architectures
  • Good understanding and mastery in PD flow using Cadence tools and basic TCL scripting.
  • Knowledge of design requirements and guidelines for automotive applications and associated analog DFT hooks is a desirable
  • High speed (up to 2Ghz) design closure experience
  • Experience/Understanding of Backend flows like Synthesis, Floorplan & Powerplan, Placement, Clock Tree Synthesis, Route, STA, Reliability & Physical verification closure.


Preferred Skills/ Experience:

  • Experienced with IC design and full development cycle from definition through release to production.
  • Effective communication skills to interact with all stakeholders.
  • Team and People Skills: The candidate should have good people skills to work closely with the systems, analog, layout and test team
  • Must be highly focused and remain committed to obtaining closure on project goals


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