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Silicon Engineering Intern at Microsoft India

  Hello Dear Readers, Currently, at Microsoft India  vacancy for Silicon Engineering Intern role. At Microsoft, Interns work on real-world projects in collaboration with teams across the world, while having fun along the way. You’ll be empowered to build community, explore your passions and achieve your goals. This is your chance to bring your solutions and ideas to life while working on cutting-edge technology. Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond. Qualifications: Currently pursuing a bachelor’s degree in Electronics Engineering, Electrical & Electronics/Computer Science Engineering.   Preferred Qualifications (PQs):   Experience or classes in t
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Physical Design Engineer at Texas Instruments

 Hello Dear Readers,

At Texas Instruments Bangalore, there is a vacancy for the Physical Design Engineer role.

The Radar and Analytics group at Texas Instruments India is looking for passionate Physical Design Engineer to work on next-gen CMOS single-chip millimeter wave sensor portfolio for Automotive Radar and Industrial applications. Physical Design team here owns Complete SoC Synthesis to Layout closure including constraints development and STA & is responsible for design handoff to manufacturing. Physical Design team at Radar & Analytics also works closely with systems and designs team for PPA optimization and has good knowledge of system aspects of the device usage. 

Responsibilities:

  • As a Physical Design Engineer in the team, you will be working independently on the entire flow from RTL to GDSII.
  • Understand the design, clock architecture, reset architecture, DFT architecture and influence them as per Physical Design needs.
  • Responsible for Place & Route, Reliability and Physical verification, Reliability closure
  • Methodologies to keep the PD cycle efficient and predictable.
  • Techniques to reduce Power and Area to make the device competitive
  • Techniques used in automotive designs.
  • Ability to interface with Fab and Qualification teams.


Minimum Qualifications:

  • Bachelor or Master’s degree in Electrical/Electronics Engineering.
  • 1-2 years of Industry experience
  • Understanding of DFT architectures
  • Good understanding and mastery in PD flow using Cadence tools and basic TCL scripting.
  • Knowledge of design requirements and guidelines for automotive applications and associated analog DFT hooks is a desirable
  • High speed (up to 2Ghz) design closure experience
  • Experience/Understanding of Backend flows like Synthesis, Floorplan & Powerplan, Placement, Clock Tree Synthesis, Route, STA, Reliability & Physical verification closure.


Preferred Skills/ Experience:

  • Experienced with IC design and full development cycle from definition through release to production.
  • Effective communication skills to interact with all stakeholders.
  • Team and People Skills: The candidate should have good people skills to work closely with the systems, analog, layout and test team
  • Must be highly focused and remain committed to obtaining closure on project goals


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