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Physical Design Methodology Engineer at Texas Instruments

  Hello Dear Readers, Texas Instruments Bangalore has a vacancy for the Physical Design Engineer role. We need an Physical Design Methodology Engineer to join our ATD team. The candidate should have a strong background in back-end design of ASIC/SoC chips. The ideal candidate will have a bachelor’s or master’s degree in Electrical Engineering or a related field. Requirements: 1 - 2 Years of experience in physical design Bachelor’s or master’s degree in Electrical/Electronics Engineering or a related field Strong understanding of physical design principles Must know the basics of floorplan, placement, CTS, routing, ECO, Physical Verification Proficiency in back-end design tools, such as Cadence Genus/Innovus/Tempus/Voltus Excellent problem-solving skills and attention to detail Effective communication and collaboration skills Responsibilities: Synthesis to GDSII Perform full Physical design flow and its verification Work closely with Digital Design and DFT engineers Ensure...
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Engineer - DV at SiFive

Hello Dear Readers, 

Currently at SiFive vacancy for ASIC Verification Engineer role.

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.


Job Description:

 

Requirement:

  • ​1-4 years of experience in DV preferably in CPU verification.
  • Proficiency in System Verilog and UVM methodology.
  • Very good object oriented programming skills.
  • Any CPU architecture knowledge (x86, ARM or RISC-V) with test-writing/test plan implementation experience.
  • Any scripting knowledge, preferably python.

Preferred skills:

  • Bus interface knowledge like AXI or PCIE
  • Integration experience with third party VIPs like bus VIPs.
  • CPU micro-arch knowledge.
  • Hands on system Verilog /UVM development work for modern high-performance CPU
  • verification.
  • Work will involve writing test cases, using test generators to generate targeted tests for RISCV CPU verification
  • Working with internal test generators to target coverage/test-plan scenarios.





Comments

  1. Anonymous29 June 2024 at 20:54

    Good opportunities for verification domain

    ReplyDelete
  2. Anonymous7 July 2024 at 02:42

    I got a call any idea about interview

    ReplyDelete

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