Skip to main content

Power Architecture Engineer at Nvidia

Hello Dear Readers,   Currently at Nvidia vacancy for Power Architecture Engineer role. NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! What you’ll be doing: Be part of NVIDIA Power Architecture Group that owns end-to-end power aspects such ...
Post a Comment

Digital Design Engineer at Analog Devices

 Hello Dear Readers,

Currently, at Analog Devices Bangalore vacancy for Digital Design Engineer role.

Analog Devices is a global leader in the design and manufacturing of integrated circuits to help solve the toughest engineering challenges. Analog Devices enables our customers to interpret the world around us by intelligently bridging the physical and digital with unmatched technologies that sense, measure and connect. We create innovative solutions to solve design challenges in instrumentation, automation, communications, healthcare, automotive and numerous other industries.

Analog Devices Inc (ADI) is looking for Digital IC Design and Verification Engineers for its Chip Design and development team in Bangalore, India.

The selected students will work on chip development based on ultra-deep submicron semiconductor process technologies. They will be guided and trained by ADI’s experienced design and verification engineers.

Responsibilities:

  • Development of key digital blocks and SoCs.
  • Development of optimal micro-architecture and design by analyzing power, performance and area tradeoffs.
  • Verification of key digital blocks and SoCs in High Speed signal converter /Communication products.
  • Definition of testplan, tests and verification methodology for block and chip-level verification.
  • They will use industry leading CAD tools.
  • Knowledge of Verilog language
  • Knowledge of digital circuit design – combination and sequential
  • Hands on any scripting languages such as perl/phyton
  • Good Analytical skills
  • Should be able to work independently and proactive

 Additional Skills being looked for:

  • System Verilog
  • Any projects on FPGA/matlab would benefit
  • Understanding of signal processing/filtering background
  • Good understanding of ADCs/DACs
  • Basic understanding of pipelining, 8085/any-other-assembly language 
Labels:

Comments

  1. Anonymous12 January 2023 at 19:12

    Is it a job drive or a direct interview?

    ReplyDelete

Post a Comment

Popular posts from this blog

Signal Electromigration (Signal EM): Violations, Examples, and Practical Fixes

  Hello Dear Readers,   Today in this post, I will provide some deep insight into the Signal Electromigration (Signal EM): Violations, Examples, and Practical Fixes. 1. Introduction: As technology nodes shrink into the deep‑submicron and nanometer regime (7nm, 5nm, 3nm and beyond), electromigration (EM) has become a first‑order reliability concern—not only for power/ground (PG) networks but also for signal nets. Signal EM failures are often underestimated because signal currents are transient and bidirectional. However, with higher switching activity, tighter metal pitches, thinner wires, and aggressive timing closure, signal EM can cause latent or early‑life failures if not addressed properly. This article explains: What Signal EM is and how it differs from PG EM Typical Signal EM violation scenarios Detailed, practical examples Root causes behind each violation Proven solutions and best practices to fix and prevent Signal EM issues 2. What is Signal Electromigration: El...
Post a Comment
Read more

Exploring the Role of LEF Files in VLSI Chip Design: A Beginner's Guide

Hello Dear Readers,   Today in this post, I will provide some deep insight into the LEF file role during the VLSI Chip Design process. In VLSI (Very Large Scale Integration) design, a LEF file is a file that contains information about the physical geometry of the standard cells used in a circuit. LEF stands for Library Exchange Format. A standard cell is a pre-designed logic cell that contains a specific function, such as a flip-flop or an AND gate. Standard cells are designed to be easily combinable and scalable to create more complex circuits. The physical geometry of each standard cell is defined in the LEF file. The LEF file contains information such as the width, height, and position of the pins and metal layers of each standard cell. It also contains information about the physical design rules that govern the placement of these cells on the chip. LEF files are important in VLSI design because they enable the interoperability of different design tools from different vend...
4 comments
Read more

Power Analysis in the VLSI Chip Design

  Hello Dear Readers,   Today in this series of posts I will provide some deep insight into Power Analysis in the VLSI Chip Design. The power analysis flow calculates (estimates of) the active and static leakage power dissipation of the SoC design. This electrical analysis step utilizes the detailed extraction model of the block and global SoC layouts. The active power estimates depend on the availability of switching factors for all signals in the cell netlist. Representative simulation test cases are applied to the netlist model, and the signal value change data are recorded. The output data from the power analysis flow guide the following SoC tape out release assessments:  Total SoC power specification (average and standby leakage): The specification for SoC power is critical for package selection and is used by end customers for thermal analysis of the product enclosure. In addition to the package technology selection, the SoC power dissipation is used to ev...
5 comments
Read more