Skip to main content

Physical Design Methodology Engineer at Texas Instruments

  Hello Dear Readers, Texas Instruments Bangalore has a vacancy for the Physical Design Engineer role. We need an Physical Design Methodology Engineer to join our ATD team. The candidate should have a strong background in back-end design of ASIC/SoC chips. The ideal candidate will have a bachelor’s or master’s degree in Electrical Engineering or a related field. Requirements: 1 - 2 Years of experience in physical design Bachelor’s or master’s degree in Electrical/Electronics Engineering or a related field Strong understanding of physical design principles Must know the basics of floorplan, placement, CTS, routing, ECO, Physical Verification Proficiency in back-end design tools, such as Cadence Genus/Innovus/Tempus/Voltus Excellent problem-solving skills and attention to detail Effective communication and collaboration skills Responsibilities: Synthesis to GDSII Perform full Physical design flow and its verification Work closely with Digital Design and DFT engineers Ensure...

CPU Hardware Architect at Imagination

 Hello Dear Readers,

Currently, Imagination has a vacancy for a CPU Hardware Architect role.

The role is for our fast-growing CPU Hardware team. We are expanding our CPU IP development from internal use to support an extensive portfolio offering highly competitive RISC-V CPUs, either as standalone IPs or as part of Imagination’s Heterogeneous Compute offering, which includes our world-class GPU and NNA compute elements. Our mission is to create through constant innovation the best-in-class RISC-V CPUs for a wide range of market segments and applications.

Reporting to the Vice President of CPU HW Engineering, we are looking for an individual with proven technical leadership and applied knowledge of various Computer and CPU architecture and micro-architecture topics.

The successful candidate will be join our CPU Architecture team which is responsible for defining the CPU micro-architecture, influencing the evolution of the RISC-V ISA and working with customers and ecosystem partners to deliver against the CPU roadmap.

You will:

    • Define the architecture and micro-architecture of Imagination CPUs to implement the required features and achieve power, performance, and area goals
    • Work with the software and hardware product engineering leadership teams to ensure that implementations meet the required goals in the required timeframe
    • Define future roadmap features and performance requirements with the Product Team
    • Work with the CPU Engineering Leadership Team and Imagination Research Team on technology pipelines and the implementation of Imagination’s Heterogenous Compute strategy
    • Liase with customers and ecosystem partners to understand future roadmap requirements
    • Coordinate activities with RISC-V International, participating in workgroups to ensure future ISA decisions are aligned with Imagination requirements
    • Help Imagination establish a leadership position in the wider RISC-V Ecosystem
    • Instigate continuous improvement of processes, and govern the engineering development flow
    • Have a proven track record of significant technical contribution to multiple and complex CPU IP developments
    • Have strong technical knowledge of CPU architecture and micro-architecture, with expert knowledge on at least one architecture domain (CPU Pipeline, CPU Memory System, Coherency, Debug and Trace etc)
    • An understanding of technology requirements for specific CPU applications including mobile, automotive and data center and the ability to translate them to product and technical requirements
    • Have strong leadership skills with the ability to influence stakeholders and inspire the engineering team
    • Be able to demonstrate effective critical analysis and proven decision-making skills, with the capability to present complex ideas in simple terms
    • Have significant experience in working and technically driving engineering teams in a global, multi-location environment
    • Be able to operate in a dynamic environment and help set the technical direction of the engineering team
    • Be able to demonstrate significant expertise in IP Design and/or Verification methodology

Comments

  1. I have already applied in it so after 2 month it is fine to apply again?

    ReplyDelete

Post a Comment

Popular posts from this blog

Best Book for Designing Microarchitecture of Microprocessor Using Verilog HDL

  Hello Dear Readers, Currently, after succeeding in many topics now I starting to provide technical book reviews which were I have completed and still read books always. So let us start today's book review. Book Name:   Computer Principles and Design in Verilog  HDL Description:  Uses Verilog HDL to illustrate computer architecture and microprocessor design, allowing readers to readily simulate and adjust the operation of each design, and thus build industrially relevant skills Introduces the computer principles, computer design, and how to use Verilog HDL (Hardware Description Language) to implement the design Provides the skills for designing processor/arithmetic/cpu chips, including the unique application of Verilog HDL material for CPU (central processing unit) implementation Despite the many books on Verilog and computer architecture and microprocessor design, few, if any, use Verilog as a key tool in helping a student to understand these design techniques...

Internship - SoC /IP Design at NXP India

Hello Dear Readers, Currently, at NXP India  vacancy for  Internship - SoC /IP Design   role.   We are looking for a Master degree student with Electronics and Communication Engineering, or related field, with an emphasis on SoC design. This is a full-time internship with a duration of about 11-12 months. Job Responsibility: Working with our experienced design team to design state of the art SoC hardware specific segment applications like Automotive, IoT, voice/object recognition, security, smart connectivity and touch sensing . Assisting experienced engineers with End-to-end ownership of SoC Design, Verification and implementation (Physical Design). Design and verify digital and Mixed-signal IPs. Document designs and present results. Job Qualification: Master student in electronic/computer engineering Creative and positive mindset Good knowledge on CMOS technologies Great communication skills, interpersonal skills, teamwork skills and can-do attitude Desire for a ca...

IC Design Engineer at Broadcom

  Hello Dear Readers, Currently, at Broadcom vacancy for an IC Design Engineer role. Job Description: Candidate would be required to work on various phases of SOC physical design activities. The job will include but not limited to block level – floor-planning, partitioning, placement, clock tree synthesis, route, physical verification (LVS/DRC/ERC/Antenna etc). Should be able to meet congestion, timing and area metrics.  Candidate would be required to do equivalence checks, STA, Crosstalk delay analysis, noise analysis, power optimization. Should be able to implement timing and functional ECOs. Should have excellent problem-solving skill to help through congestion resolution and timing closure. Should have experience formal verification and timing analysis and ECO implementation. Experience with tools such as Innovus/Encounter, ICC, Caliber, LEC, Primetime etc is highly desirable. Candidate should be able to work independently and guide other team members. Should be ...