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VLSI Packaging Evolution and Innovations

Hello Dear Readers,   Today in this post, I will provide some deep insight into the VLSI packaging evolution and innovations. Semiconductor packaging has evolved from a simple protective housing into a critical performance enabler. In the modern VLSI landscape, packaging is no longer an afterthought; it is a fundamental determinant of PPA (Power, Performance, and Area) metrics, often dictating the thermal limits and signal integrity of the final SoC. 1. Traditional Packaging Technologies: These methods are the workhorses of the industry, widely used for low-to-medium complexity devices where cost-efficiency is paramount. Wire Bonding (QFN, QFP, DIP): Wire bonding is the most mature interconnection technology. It uses thin gold, copper, or aluminum wires to connect the die's bond pads to the package's internal leadframe. Implementation: The die is attached face-up to a leadframe or substrate. A wire bonder uses thermocompression or ultrasonic energy to attach wires betwee...
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CPU Hardware Architect at Imagination

 Hello Dear Readers,

Currently, Imagination has a vacancy for a CPU Hardware Architect role.

The role is for our fast-growing CPU Hardware team. We are expanding our CPU IP development from internal use to support an extensive portfolio offering highly competitive RISC-V CPUs, either as standalone IPs or as part of Imagination’s Heterogeneous Compute offering, which includes our world-class GPU and NNA compute elements. Our mission is to create through constant innovation the best-in-class RISC-V CPUs for a wide range of market segments and applications.

Reporting to the Vice President of CPU HW Engineering, we are looking for an individual with proven technical leadership and applied knowledge of various Computer and CPU architecture and micro-architecture topics.

The successful candidate will be join our CPU Architecture team which is responsible for defining the CPU micro-architecture, influencing the evolution of the RISC-V ISA and working with customers and ecosystem partners to deliver against the CPU roadmap.

You will:

    • Define the architecture and micro-architecture of Imagination CPUs to implement the required features and achieve power, performance, and area goals
    • Work with the software and hardware product engineering leadership teams to ensure that implementations meet the required goals in the required timeframe
    • Define future roadmap features and performance requirements with the Product Team
    • Work with the CPU Engineering Leadership Team and Imagination Research Team on technology pipelines and the implementation of Imagination’s Heterogenous Compute strategy
    • Liase with customers and ecosystem partners to understand future roadmap requirements
    • Coordinate activities with RISC-V International, participating in workgroups to ensure future ISA decisions are aligned with Imagination requirements
    • Help Imagination establish a leadership position in the wider RISC-V Ecosystem
    • Instigate continuous improvement of processes, and govern the engineering development flow
    • Have a proven track record of significant technical contribution to multiple and complex CPU IP developments
    • Have strong technical knowledge of CPU architecture and micro-architecture, with expert knowledge on at least one architecture domain (CPU Pipeline, CPU Memory System, Coherency, Debug and Trace etc)
    • An understanding of technology requirements for specific CPU applications including mobile, automotive and data center and the ability to translate them to product and technical requirements
    • Have strong leadership skills with the ability to influence stakeholders and inspire the engineering team
    • Be able to demonstrate effective critical analysis and proven decision-making skills, with the capability to present complex ideas in simple terms
    • Have significant experience in working and technically driving engineering teams in a global, multi-location environment
    • Be able to operate in a dynamic environment and help set the technical direction of the engineering team
    • Be able to demonstrate significant expertise in IP Design and/or Verification methodology

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  1. Anonymous12 November 2022 at 09:53

    I have already applied in it so after 2 month it is fine to apply again?

    ReplyDelete

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