Skip to main content

SRAM/Memory CAD Engineer at Qualcomm

  Hello Dear Readers, Qualcomm Bangalore currently has a vacancy for an SRAM/Memory CAD Engineer. As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems,  Digital/Analog/RF/optical  systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: • Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronic...
Post a Comment

CPU Hardware Architect at Imagination

 Hello Dear Readers,

Currently, Imagination has a vacancy for a CPU Hardware Architect role.

The role is for our fast-growing CPU Hardware team. We are expanding our CPU IP development from internal use to support an extensive portfolio offering highly competitive RISC-V CPUs, either as standalone IPs or as part of Imagination’s Heterogeneous Compute offering, which includes our world-class GPU and NNA compute elements. Our mission is to create through constant innovation the best-in-class RISC-V CPUs for a wide range of market segments and applications.

Reporting to the Vice President of CPU HW Engineering, we are looking for an individual with proven technical leadership and applied knowledge of various Computer and CPU architecture and micro-architecture topics.

The successful candidate will be join our CPU Architecture team which is responsible for defining the CPU micro-architecture, influencing the evolution of the RISC-V ISA and working with customers and ecosystem partners to deliver against the CPU roadmap.

You will:

    • Define the architecture and micro-architecture of Imagination CPUs to implement the required features and achieve power, performance, and area goals
    • Work with the software and hardware product engineering leadership teams to ensure that implementations meet the required goals in the required timeframe
    • Define future roadmap features and performance requirements with the Product Team
    • Work with the CPU Engineering Leadership Team and Imagination Research Team on technology pipelines and the implementation of Imagination’s Heterogenous Compute strategy
    • Liase with customers and ecosystem partners to understand future roadmap requirements
    • Coordinate activities with RISC-V International, participating in workgroups to ensure future ISA decisions are aligned with Imagination requirements
    • Help Imagination establish a leadership position in the wider RISC-V Ecosystem
    • Instigate continuous improvement of processes, and govern the engineering development flow
    • Have a proven track record of significant technical contribution to multiple and complex CPU IP developments
    • Have strong technical knowledge of CPU architecture and micro-architecture, with expert knowledge on at least one architecture domain (CPU Pipeline, CPU Memory System, Coherency, Debug and Trace etc)
    • An understanding of technology requirements for specific CPU applications including mobile, automotive and data center and the ability to translate them to product and technical requirements
    • Have strong leadership skills with the ability to influence stakeholders and inspire the engineering team
    • Be able to demonstrate effective critical analysis and proven decision-making skills, with the capability to present complex ideas in simple terms
    • Have significant experience in working and technically driving engineering teams in a global, multi-location environment
    • Be able to operate in a dynamic environment and help set the technical direction of the engineering team
    • Be able to demonstrate significant expertise in IP Design and/or Verification methodology

Labels:

Comments

  1. Anonymous12 November 2022 at 09:53

    I have already applied in it so after 2 month it is fine to apply again?

    ReplyDelete

Post a Comment

Popular posts from this blog

Internship - SoC /IP Design at NXP India

Hello Dear Readers, Currently, at NXP India  vacancy for  Internship - SoC /IP Design   role.   We are looking for a Master degree student with Electronics and Communication Engineering, or related field, with an emphasis on SoC design. This is a full-time internship with a duration of about 11-12 months. Job Responsibility: Working with our experienced design team to design state of the art SoC hardware specific segment applications like Automotive, IoT, voice/object recognition, security, smart connectivity and touch sensing . Assisting experienced engineers with End-to-end ownership of SoC Design, Verification and implementation (Physical Design). Design and verify digital and Mixed-signal IPs. Document designs and present results. Job Qualification: Master student in electronic/computer engineering Creative and positive mindset Good knowledge on CMOS technologies Great communication skills, interpersonal skills, teamwork skills and can-do attitude Desire for a ca...
Post a Comment
Read more

Best Book for Designing Microarchitecture of Microprocessor Using Verilog HDL

  Hello Dear Readers, Currently, after succeeding in many topics now I starting to provide technical book reviews which were I have completed and still read books always. So let us start today's book review. Book Name:   Computer Principles and Design in Verilog  HDL Description:  Uses Verilog HDL to illustrate computer architecture and microprocessor design, allowing readers to readily simulate and adjust the operation of each design, and thus build industrially relevant skills Introduces the computer principles, computer design, and how to use Verilog HDL (Hardware Description Language) to implement the design Provides the skills for designing processor/arithmetic/cpu chips, including the unique application of Verilog HDL material for CPU (central processing unit) implementation Despite the many books on Verilog and computer architecture and microprocessor design, few, if any, use Verilog as a key tool in helping a student to understand these design techniques...
3 comments
Read more

Exploring the Role of LEF Files in VLSI Chip Design: A Beginner's Guide

Hello Dear Readers,   Today in this post, I will provide some deep insight into the LEF file role during the VLSI Chip Design process. In VLSI (Very Large Scale Integration) design, a LEF file is a file that contains information about the physical geometry of the standard cells used in a circuit. LEF stands for Library Exchange Format. A standard cell is a pre-designed logic cell that contains a specific function, such as a flip-flop or an AND gate. Standard cells are designed to be easily combinable and scalable to create more complex circuits. The physical geometry of each standard cell is defined in the LEF file. The LEF file contains information such as the width, height, and position of the pins and metal layers of each standard cell. It also contains information about the physical design rules that govern the placement of these cells on the chip. LEF files are important in VLSI design because they enable the interoperability of different design tools from different vend...
4 comments
Read more