Skip to main content

Design Engineer - STA, SD, Power, PDN at Dew Software

Hello Dear Readers,   Currently at Dew Software Bangalore vacancy for Design Engineer - STA, SD, Power, PDN role. Dew Software, a leading player in the Digital Transformation space, is seeking a skilled Design Engineer specializing in STA (Static Timing Analysis), SD (Signal Integrity), Power, and PDN (Power Delivery Network) to join our team. Working with Fortune 500 companies to support their digital innovation and transformation strategies, the Design Engineer will be responsible for ensuring the integrity and efficiency of digital designs through comprehensive analysis and optimization. Dew Software is dedicated to delivering exceptional outcomes with cutting-edge technologies, and this is an excellent opportunity to contribute to the growth and success of our clients. Responsibilities: Perform STA (Static Timing Analysis) to ensure design meets timing requirements Conduct signal integrity analysis to optimize signal integrity and minimize signal integrity issues Provide power anal

CPU Hardware Architect at Imagination

 Hello Dear Readers,

Currently, Imagination has a vacancy for a CPU Hardware Architect role.

The role is for our fast-growing CPU Hardware team. We are expanding our CPU IP development from internal use to support an extensive portfolio offering highly competitive RISC-V CPUs, either as standalone IPs or as part of Imagination’s Heterogeneous Compute offering, which includes our world-class GPU and NNA compute elements. Our mission is to create through constant innovation the best-in-class RISC-V CPUs for a wide range of market segments and applications.

Reporting to the Vice President of CPU HW Engineering, we are looking for an individual with proven technical leadership and applied knowledge of various Computer and CPU architecture and micro-architecture topics.

The successful candidate will be join our CPU Architecture team which is responsible for defining the CPU micro-architecture, influencing the evolution of the RISC-V ISA and working with customers and ecosystem partners to deliver against the CPU roadmap.

You will:

    • Define the architecture and micro-architecture of Imagination CPUs to implement the required features and achieve power, performance, and area goals
    • Work with the software and hardware product engineering leadership teams to ensure that implementations meet the required goals in the required timeframe
    • Define future roadmap features and performance requirements with the Product Team
    • Work with the CPU Engineering Leadership Team and Imagination Research Team on technology pipelines and the implementation of Imagination’s Heterogenous Compute strategy
    • Liase with customers and ecosystem partners to understand future roadmap requirements
    • Coordinate activities with RISC-V International, participating in workgroups to ensure future ISA decisions are aligned with Imagination requirements
    • Help Imagination establish a leadership position in the wider RISC-V Ecosystem
    • Instigate continuous improvement of processes, and govern the engineering development flow
    • Have a proven track record of significant technical contribution to multiple and complex CPU IP developments
    • Have strong technical knowledge of CPU architecture and micro-architecture, with expert knowledge on at least one architecture domain (CPU Pipeline, CPU Memory System, Coherency, Debug and Trace etc)
    • An understanding of technology requirements for specific CPU applications including mobile, automotive and data center and the ability to translate them to product and technical requirements
    • Have strong leadership skills with the ability to influence stakeholders and inspire the engineering team
    • Be able to demonstrate effective critical analysis and proven decision-making skills, with the capability to present complex ideas in simple terms
    • Have significant experience in working and technically driving engineering teams in a global, multi-location environment
    • Be able to operate in a dynamic environment and help set the technical direction of the engineering team
    • Be able to demonstrate significant expertise in IP Design and/or Verification methodology

Comments

  1. I have already applied in it so after 2 month it is fine to apply again?

    ReplyDelete

Post a Comment

Popular posts from this blog

Apprenticeship CAI at MediaTek Bangalore

Hello Dear Readers,   Currently at MediaTek Bangalore vacancy for an Apprenticeship CAI role. Job Description: B.Tech degree in Electrical/Electronics Engineering with a strong educational background in Digital circuit design Experience in physical design of high performance design with frequencies > 2 Ghz. Experienced in hierarchical design, budgeting, multiple voltage domains and multiple clock domains. Strong skills with Cadence Encounter. Solid understanding of STA and timing constraints. Experienced in working on advanced process nodes (16nm). Strong expertise in Physical Verification to debug LVS/DRC issues at the block level. Requirement: B.Tech degree in Electrical/Electronics Engineering with strong educational background in Digital circuit design Experience in physical design of high performance design with frequencies > 2 Ghz. Experienced in hierarchical design, budgeting, multiple voltage domains and multiple clock domains. Strong skills with Cadence Encounter. Solid

Power Analysis in the VLSI Chip Design

  Hello Dear Readers,   Today in this series of posts I will provide some deep insight into Power Analysis in the VLSI Chip Design. The power analysis flow calculates (estimates of) the active and static leakage power dissipation of the SoC design. This electrical analysis step utilizes the detailed extraction model of the block and global SoC layouts. The active power estimates depend on the availability of switching factors for all signals in the cell netlist. Representative simulation test cases are applied to the netlist model, and the signal value change data are recorded. The output data from the power analysis flow guide the following SoC tape out release assessments:  Total SoC power specification (average and standby leakage): The specification for SoC power is critical for package selection and is used by end customers for thermal analysis of the product enclosure. In addition to the package technology selection, the SoC power dissipation is used to evaluate the die attach ma

IC Physical Design (PnR) at Ulkasemi

Hello Dear Readers,   Ulkasemi  has a vacancy for an IC Physical Design (PnR) role. Job Overview: As a full-time Trainee Engineer, the individual will be working on IC Physical Design implementation from RTL to GDSII to create design databases ready for manufacturing with a special focus on power, performance & area optimization with next-generation state-of-the-art process technologies. Job Responsibilities: Perform physical design implementation which includes Floor planning, Power Planning, Clock Tree Synthesis, Place and Route, ECO, Logic Equivalence checks Timing analysis, physical & electrical verification, driving the sign-off closure meeting schedule, and design goals Develop flow, methodologies, and automation scripts for various implementation steps Follow the instructions, compile documents, prepare deliverables, and report to the team lead Should remain up to date with the latest technology trends Educational Qualification:   B.Sc/M.Sc   in EEE or equivalent degree