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ASIC Physical Design Engineer at HPE

 Hello Dear Readers,

At HPE Bangalore, there is a vacancy for a Physical Design Engineer role.

This role has been designed as ‘’Onsite’ with an expectation that you will primarily work from an HPE office.

Who We Are:

Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world. Our culture thrives on finding new and better ways to accelerate what’s next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE.

Job Description:

Aruba is an HPE Company, and a leading provider of next-generation network access solutions for the mobile enterprise. Helping some of the largest companies in the world modernize their networks to meet the demands of a digital future, Aruba is redefining the “Intelligent Edge” – and creating new customer experiences across intelligent spaces and digital workspaces. Join us redefine what’s next for you.

Seeking a hands-on ASIC Physical Design Engineer with strong expertise in physical design implementation, flow development, methodology ownership, and scripting automation to enable robust and scalable ASIC delivery.

What you'll do:

  • Execute end-to-end physical design: floorplanning, placement, CTS, routing, and physical closure.
  • Contribute to and improve ASIC physical design flows and methodologies at block and full-chip levels.
  • Develop, maintain, and optimize PD automation using Tcl/Python to improve QoR, productivity, and turnaround time.
  • Support timing, congestion, and PPA optimization, and drive implementation issues to closure.
  • Work closely with STA, DFT, and sign-off teams to ensure smooth integration and tape-out readiness.

What you need to bring:

  • 4–6 years of hands-on experience in ASIC Physical Design implementation.
  • Strong knowledge of PD flows and methodologies using tools such as ICC2/Fusion Compiler/Innovus.
  • Solid understanding of timing concepts, CTS, ECOs, and physical closure.
  • Proficiency in Tcl and Python scripting for flow automation and data analysis is a must.
  • Ability to debug complex PD issues and contribute to continuous flow improvements.

Education:

B.Tech / M.Tech in Electronics, VLSI, or related fields.


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