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Physical Design/PDK methodology Engineer

Hello Dear Readers, At Applied Materials Bangalore, there is a vacancy for a Physical Design/PDK methodology Engineer role. Applied Materials is a global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service cutting-edge equipment that helps our customers manufacture display and semiconductor chips – the brains of devices we use every day. As the foundation of the global electronics industry, Applied enables the exciting technologies that literally connect our world – like AI and IoT. If you want to push the boundaries of materials science and engineering to create next generation technology, join us to deliver material innovation that changes the world.  Key Responsibility: Expertise in PDK enablement and library  validation/automation. Hands-on experience with LVS/Parasitic extraction/standard cell characterization flows and methodologies Design/System level experience with DTCO and ...
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Senior Physical Design Engineer at Samsung Electronics

Hello Dear Readers,

Currently, at Samsung Electronics Bangalore vacancy for a Senior Physical Design Engineer role.

About the job:

Complex SOC Top Physical Implementation for next generation SoCs in area of mobile application processors, modem sub-systems and connectivity chips

by means of Synthesis , Place and Route, STA , timing and physical signoffs


  •  Hands-on experience doing physical design and timing closure of complex blocks and full-chip designs
  • Should have strong understanding of timing, power, and area trade-offs and optimization of PPA
  • Power user of industry-standard tools (ICC/DC/PT/VSLP/Redhawk/Calibre/Formality) and able to understand their capabilities
  • Should have solid understanding of scripting languages such as Perl/Tcl and implementation flows
  • Experience with large SOC designs (>20M gates) with frequencies in excess of 1GHZ .
  • Expertise in block level and full-chip SDC cleanup, Synthesis optimization, Low Power checking and logic equivalence checking
  • Familiar with deep sub-micron designs (8nm/5nm) and associated issues (manufacturability, power, signal integrity, scaling)
  • Familiar with typical SoC issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration, and package interactions.
  • Familiar in a hierarchical design, top-down design, budgeting, timing, and physical convergence
  • Experience in top level floor planning including partition shaping and sizing, pin placement, channel planning,
  • high-speed signal and clock planning and feed-through planning is a plus
  • Good understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level
  • Should have gone through recent successful SoC tape-outs
  • Should have 3 ~ 15 years of experience in physical implementation and design

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