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Product Engineer II at Cadence Design Systems

Hello Dear Readers, Cadence Design Systems has a vacancy for a Product Engineer II role. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.  Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage: The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recog...
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Senior Physical Design Engineer at Samsung Electronics

Hello Dear Readers,

Currently, at Samsung Electronics Bangalore vacancy for a Senior Physical Design Engineer role.

About the job:

Complex SOC Top Physical Implementation for next generation SoCs in area of mobile application processors, modem sub-systems and connectivity chips

by means of Synthesis , Place and Route, STA , timing and physical signoffs


  •  Hands-on experience doing physical design and timing closure of complex blocks and full-chip designs
  • Should have strong understanding of timing, power, and area trade-offs and optimization of PPA
  • Power user of industry-standard tools (ICC/DC/PT/VSLP/Redhawk/Calibre/Formality) and able to understand their capabilities
  • Should have solid understanding of scripting languages such as Perl/Tcl and implementation flows
  • Experience with large SOC designs (>20M gates) with frequencies in excess of 1GHZ .
  • Expertise in block level and full-chip SDC cleanup, Synthesis optimization, Low Power checking and logic equivalence checking
  • Familiar with deep sub-micron designs (8nm/5nm) and associated issues (manufacturability, power, signal integrity, scaling)
  • Familiar with typical SoC issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration, and package interactions.
  • Familiar in a hierarchical design, top-down design, budgeting, timing, and physical convergence
  • Experience in top level floor planning including partition shaping and sizing, pin placement, channel planning,
  • high-speed signal and clock planning and feed-through planning is a plus
  • Good understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level
  • Should have gone through recent successful SoC tape-outs
  • Should have 3 ~ 15 years of experience in physical implementation and design

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