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VLSI Packaging Evolution and Innovations

Hello Dear Readers,   Today in this post, I will provide some deep insight into the VLSI packaging evolution and innovations. Semiconductor packaging has evolved from a simple protective housing into a critical performance enabler. In the modern VLSI landscape, packaging is no longer an afterthought; it is a fundamental determinant of PPA (Power, Performance, and Area) metrics, often dictating the thermal limits and signal integrity of the final SoC. 1. Traditional Packaging Technologies: These methods are the workhorses of the industry, widely used for low-to-medium complexity devices where cost-efficiency is paramount. Wire Bonding (QFN, QFP, DIP): Wire bonding is the most mature interconnection technology. It uses thin gold, copper, or aluminum wires to connect the die's bond pads to the package's internal leadframe. Implementation: The die is attached face-up to a leadframe or substrate. A wire bonder uses thermocompression or ultrasonic energy to attach wires betwee...
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Senior Physical Design Engineer at Samsung Electronics

Hello Dear Readers,

Currently, at Samsung Electronics Bangalore vacancy for a Senior Physical Design Engineer role.

About the job:

Complex SOC Top Physical Implementation for next generation SoCs in area of mobile application processors, modem sub-systems and connectivity chips

by means of Synthesis , Place and Route, STA , timing and physical signoffs


  •  Hands-on experience doing physical design and timing closure of complex blocks and full-chip designs
  • Should have strong understanding of timing, power, and area trade-offs and optimization of PPA
  • Power user of industry-standard tools (ICC/DC/PT/VSLP/Redhawk/Calibre/Formality) and able to understand their capabilities
  • Should have solid understanding of scripting languages such as Perl/Tcl and implementation flows
  • Experience with large SOC designs (>20M gates) with frequencies in excess of 1GHZ .
  • Expertise in block level and full-chip SDC cleanup, Synthesis optimization, Low Power checking and logic equivalence checking
  • Familiar with deep sub-micron designs (8nm/5nm) and associated issues (manufacturability, power, signal integrity, scaling)
  • Familiar with typical SoC issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration, and package interactions.
  • Familiar in a hierarchical design, top-down design, budgeting, timing, and physical convergence
  • Experience in top level floor planning including partition shaping and sizing, pin placement, channel planning,
  • high-speed signal and clock planning and feed-through planning is a plus
  • Good understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level
  • Should have gone through recent successful SoC tape-outs
  • Should have 3 ~ 15 years of experience in physical implementation and design

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