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Physical Design Methodology Engineer at Texas Instruments

  Hello Dear Readers, Texas Instruments Bangalore has a vacancy for the Physical Design Engineer role. We need an Physical Design Methodology Engineer to join our ATD team. The candidate should have a strong background in back-end design of ASIC/SoC chips. The ideal candidate will have a bachelor’s or master’s degree in Electrical Engineering or a related field. Requirements: 1 - 2 Years of experience in physical design Bachelor’s or master’s degree in Electrical/Electronics Engineering or a related field Strong understanding of physical design principles Must know the basics of floorplan, placement, CTS, routing, ECO, Physical Verification Proficiency in back-end design tools, such as Cadence Genus/Innovus/Tempus/Voltus Excellent problem-solving skills and attention to detail Effective communication and collaboration skills Responsibilities: Synthesis to GDSII Perform full Physical design flow and its verification Work closely with Digital Design and DFT engineers Ensure...
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Senior Physical Design Engineer at Samsung Electronics

Hello Dear Readers,

Currently, at Samsung Electronics Bangalore vacancy for a Senior Physical Design Engineer role.

About the job:

Complex SOC Top Physical Implementation for next generation SoCs in area of mobile application processors, modem sub-systems and connectivity chips

by means of Synthesis , Place and Route, STA , timing and physical signoffs


  •  Hands-on experience doing physical design and timing closure of complex blocks and full-chip designs
  • Should have strong understanding of timing, power, and area trade-offs and optimization of PPA
  • Power user of industry-standard tools (ICC/DC/PT/VSLP/Redhawk/Calibre/Formality) and able to understand their capabilities
  • Should have solid understanding of scripting languages such as Perl/Tcl and implementation flows
  • Experience with large SOC designs (>20M gates) with frequencies in excess of 1GHZ .
  • Expertise in block level and full-chip SDC cleanup, Synthesis optimization, Low Power checking and logic equivalence checking
  • Familiar with deep sub-micron designs (8nm/5nm) and associated issues (manufacturability, power, signal integrity, scaling)
  • Familiar with typical SoC issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration, and package interactions.
  • Familiar in a hierarchical design, top-down design, budgeting, timing, and physical convergence
  • Experience in top level floor planning including partition shaping and sizing, pin placement, channel planning,
  • high-speed signal and clock planning and feed-through planning is a plus
  • Good understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level
  • Should have gone through recent successful SoC tape-outs
  • Should have 3 ~ 15 years of experience in physical implementation and design

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