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SoC RTL Design Engineer at Texas Instruments

  Hello Dear Readers, At Texas Instruments Bangalore, there is a vacancy for SoC RTL Design Engineer role. Are you looking for a career at one of the leading semiconductor companies in the world Texas Instruments (TI) is looking for a SoC RTL Design Engineer to join the team of enthusiastic engineers who develops highly complex mixed signal devices for audio applications with industry leading performance. These audio products are truly mixed-signal devices with highly integrated digital circuits such as a DSP core for digital filters and audio signal processing blocks, hardware processing blocks, analog controllers, various serial interfaces (Audio serial interfaces, I2C, SPI) and other digital blocks like clock-generation, registers map, Interrupts etc. This is a great opportunity to be part of an established team that’s continuing to look for growth opportunities, working with worldwide leading customers and developing cutting edge solutions in the areas of consumer electr...
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Senior Physical Design Engineer at Samsung Electronics

Hello Dear Readers,

Currently, at Samsung Electronics Bangalore vacancy for a Senior Physical Design Engineer role.

About the job:

Complex SOC Top Physical Implementation for next generation SoCs in area of mobile application processors, modem sub-systems and connectivity chips

by means of Synthesis , Place and Route, STA , timing and physical signoffs


  •  Hands-on experience doing physical design and timing closure of complex blocks and full-chip designs
  • Should have strong understanding of timing, power, and area trade-offs and optimization of PPA
  • Power user of industry-standard tools (ICC/DC/PT/VSLP/Redhawk/Calibre/Formality) and able to understand their capabilities
  • Should have solid understanding of scripting languages such as Perl/Tcl and implementation flows
  • Experience with large SOC designs (>20M gates) with frequencies in excess of 1GHZ .
  • Expertise in block level and full-chip SDC cleanup, Synthesis optimization, Low Power checking and logic equivalence checking
  • Familiar with deep sub-micron designs (8nm/5nm) and associated issues (manufacturability, power, signal integrity, scaling)
  • Familiar with typical SoC issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration, and package interactions.
  • Familiar in a hierarchical design, top-down design, budgeting, timing, and physical convergence
  • Experience in top level floor planning including partition shaping and sizing, pin placement, channel planning,
  • high-speed signal and clock planning and feed-through planning is a plus
  • Good understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level
  • Should have gone through recent successful SoC tape-outs
  • Should have 3 ~ 15 years of experience in physical implementation and design

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