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Physical Design Methodology Engineer at Texas Instruments

  Hello Dear Readers, Texas Instruments Bangalore has a vacancy for the Physical Design Engineer role. We need an Physical Design Methodology Engineer to join our ATD team. The candidate should have a strong background in back-end design of ASIC/SoC chips. The ideal candidate will have a bachelor’s or master’s degree in Electrical Engineering or a related field. Requirements: 1 - 2 Years of experience in physical design Bachelor’s or master’s degree in Electrical/Electronics Engineering or a related field Strong understanding of physical design principles Must know the basics of floorplan, placement, CTS, routing, ECO, Physical Verification Proficiency in back-end design tools, such as Cadence Genus/Innovus/Tempus/Voltus Excellent problem-solving skills and attention to detail Effective communication and collaboration skills Responsibilities: Synthesis to GDSII Perform full Physical design flow and its verification Work closely with Digital Design and DFT engineers Ensure...
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Design Verification Engineer at Micron Technology

 Hello Dear Readers, 

Currently, at Micron Technology vacancy for Design Verification Engineer role.

Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing.


Responsibilities will include, but are not limited to:

  • Full-chip functional verification on Micron’s non-volatile memory design projects
  • You thoroughly understand design specs and develop verification plans for various designs
  • TestBench Development in SystemVerilog targeting complete functionality coverage.
  • Create functional coverage code for assigned features
  • Support of SystemVerilog assertion and coverage-driven methodology
  • Support of design verification methodology improvements
  • Run directed and constrained-random verification tests
  • You will think through design corner cases and be able to write relevant cover points
  • Collaborate with digital design team to debug test cases and deliver functionally accurate designs
  • Close coverage measures to identify verification holes and to show progress towards tape-out
  • Driving innovation into the future Memory generations within a dynamic work environment

Minimum Qualifications:

  • MS degree in Electrical Engineering or BS with 3 years’ experience required. 
  • Design experience of 2+ years is desirable. 
  • 0- 7 of experience developing verification collateral in Verilog, System Verilog and UVM
  • UVM Proficiency is desired
  • Prior work experience with complex coverage driven random constraint UVM environment
  • Putting together complex UVM environments from scratch is a requirement
  • Good knowledge on circuit design, digital logic, and logic verification methodology
  • Understanding on Verilog RTL coding, SystemVerilog object-oriented language
  • Good knowledge on programming language such as C++, and scripting language like TCL and PERL

About Micron Technology, Inc.

We are an industry leader in innovative memory and storage solutions, transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.


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