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Physical Design Methodology Engineer at Texas Instruments

  Hello Dear Readers, Texas Instruments Bangalore has a vacancy for the Physical Design Engineer role. We need an Physical Design Methodology Engineer to join our ATD team. The candidate should have a strong background in back-end design of ASIC/SoC chips. The ideal candidate will have a bachelor’s or master’s degree in Electrical Engineering or a related field. Requirements: 1 - 2 Years of experience in physical design Bachelor’s or master’s degree in Electrical/Electronics Engineering or a related field Strong understanding of physical design principles Must know the basics of floorplan, placement, CTS, routing, ECO, Physical Verification Proficiency in back-end design tools, such as Cadence Genus/Innovus/Tempus/Voltus Excellent problem-solving skills and attention to detail Effective communication and collaboration skills Responsibilities: Synthesis to GDSII Perform full Physical design flow and its verification Work closely with Digital Design and DFT engineers Ensure...
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Application Specific Integrated Circuit Design Engineer at AumRaj Design Systems

 Hello Dear Readers, 

Currently at AumRaj Design Systems vacancy for Application Specific Integrated Circuit Design Engineer role.

Responsibilities:

  • Design and implement verification test plans, test benches, assertions, coverage, infrastructure, and platforms.
  • Work with ASIC designers, and architects to produce thoroughly verified robust IP products.
  • Develop and improve existing verification flows and methodologies in collaboration with other verification team members. Assist with bring-up and debugging of hardware projects.

Qualifications:
  • BS/BE or MS/ME degree in EC or computer engineering or closely related degree strongly preferred; but substantial, relevant, outstanding work experience may substitute in some cases.
  • Strong written and verbal communication skills in English.
  • Solid understanding of standard ASIC verification techniques, including Test planning
  • Testbench creation
  • Code and Functional coverage
  • Directed and random stimulus generation Assertions
  • Solid understanding of verification methodologies and one or more of the following standard testbench languages: System Verilog (OVM/UVM)
  • C/C++
  • Comfortable in a Unix development environment (make, scripting, SVN, etc.)
Personal Attributes:
  • Able and willing to work in a team-oriented, collaborative environment
  • A demonstrated ability to prioritize and execute tasks so as to achieve goals in an innovative, fast-paced, and often high-pressure environment
  • Proven analytical and creative problem-solving abilities.
  • Passionate about writing clean and neat code that adheres to coding guidelines.

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