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YAML in Semiconductor EDA: From Configuration Language to Reusable Design-Flow Methodology

Hello Dear Readers,   Today in this post, I will provide some deep insight about yaml langauge for CAD flow developments with detailed examples. YAML is not a programming language in the same sense as Python, Tcl, C++, or Verilog. It is primarily a human-readable data serialization/configuration language . In semiconductor EDA, that distinction is important because YAML generally describes what a flow should do , while Python/Tcl/Shell and the EDA tools execute the flow . The official YAML specification describes it as a data serialization language designed to be human-friendly and portable across programming languages. For the semiconductor angle, this becomes particularly interesting because YAML can act as a configuration layer between design methodology and EDA implementation . Frameworks such as Hammer explicitly use YAML/JSON configuration and an intermediate representation to standardize information exchanged between design, technology, and tool plugins. 1. Introduction M...
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Application Specific Integrated Circuit Design Engineer at AumRaj Design Systems

 Hello Dear Readers, 

Currently at AumRaj Design Systems vacancy for Application Specific Integrated Circuit Design Engineer role.

Responsibilities:

  • Design and implement verification test plans, test benches, assertions, coverage, infrastructure, and platforms.
  • Work with ASIC designers, and architects to produce thoroughly verified robust IP products.
  • Develop and improve existing verification flows and methodologies in collaboration with other verification team members. Assist with bring-up and debugging of hardware projects.

Qualifications:
  • BS/BE or MS/ME degree in EC or computer engineering or closely related degree strongly preferred; but substantial, relevant, outstanding work experience may substitute in some cases.
  • Strong written and verbal communication skills in English.
  • Solid understanding of standard ASIC verification techniques, including Test planning
  • Testbench creation
  • Code and Functional coverage
  • Directed and random stimulus generation Assertions
  • Solid understanding of verification methodologies and one or more of the following standard testbench languages: System Verilog (OVM/UVM)
  • C/C++
  • Comfortable in a Unix development environment (make, scripting, SVN, etc.)
Personal Attributes:
  • Able and willing to work in a team-oriented, collaborative environment
  • A demonstrated ability to prioritize and execute tasks so as to achieve goals in an innovative, fast-paced, and often high-pressure environment
  • Proven analytical and creative problem-solving abilities.
  • Passionate about writing clean and neat code that adheres to coding guidelines.

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