STANDARD CELL LIBRARY LAYOUT DESIGN - PART-1

  Hello Dear Readers, 

Today in this entire series I will give you an idea about how the standard cells library which included layout design of the basics all the gates and circuits is formed.

The growing demand for the integration of systems with the maximum possible functionality by combining high performance with a tolerable amount of power dissipation has been driving the development and the modeling of CMOS transistor technologies, especially with the growth of the embedded and portable devices market. The need for integration of more and more components onto a single chip, by improving performance with reasonable energy loss, motivated the migration to the deep sub-micron regime. The key success factor for the rapid growth of the integrated system is the use of ASIC library for various system functions. It consists of pre-designed and pre-verified logic blocks that help designers to shorten product development time and manage the complexity of a chip having millions of logic gates or more. In semiconductor design, standard cell methodology is a method of designing Application Specific Integrated Circuits (ASICs) with mostly digital-logic features. Standard cell methodology is an example of design abstraction, whereby a low level VLSI-layout is encapsulated into an abstract logic representation (such as NAND gate). Cell-based methodology (the general class that standard-cell belongs to) makes it possible for one designer to focus on the high level (logical function) aspect of digital-design, while another designer focused on the implementation (physical) aspect. Along with semiconductor manufacturing advances, standard cell methodology was responsible for allowing designers to scale ASICs from comparatively simple single function ICs (of several thousand gates), to complex multimillion gate devices (SoC). A 2-input NAND or NOR function is sufficient to form any arbitrary Boolean function set. But in modern ASIC design, standard cell methodology is practiced with a sizeable library (or libraries) of cells. The library usually contains multiple implementations of the same logic function, differing in area and speed. This variety enhances the efficiency of automated synthesis, place and route (SPR) tools. Indirectly, it also gives the designer greater freedom to perform implementation trade-offs (area vs. speed vs. power consumption). A complete group of standard cell descriptions is commonly called a technology library. The economic and efficient accomplishment of an ASIC design depends heavily upon the choice of the library. Therefore it is important to build library that full fills the design requirement. IC development is nowadays a huge industry. There is an almost infinite amount of consumer products like mobile phones, processors, televisions, cameras, refrigerators, ovens and cars that in one way or another uses custom IC components. Integrated circuits can provide anything from analog-to-digital conversion to digital filtering and much more. A digital integrated circuit can be manufactured with a number of different approaches, but they all contain the same basic steps. It all starts with transistors, wiring and all the things that make up the circuit being placed in a layout, designed in a CAD (Computer Aided Design) tool and ends up with that layout being physically created on a chip. The way to create this layout differs depending on design requirements. There are three basic ways to go about, 

i). Full Custom Design: 

When everything in the layout is created manually. Every single transistor used can be set up as desired, optimized for speed, area or capacitive load etc. Every single wire in the layout is placed manually and the designer has total control over the layout. This is done when the design has very strict requirements and needs to be optimized in one way or another. The obvious advantage is that the layout can be created very carefully to fit the need. On the other hand, this requires a lot of work and time.

ii). Semi-Custom Design: 

When the designer works on a logical gate level. This means that the designer can use gates like nand, inverters, buffers, flip-flops etc. that have already been created and distributed as a cell library by a supplier. The idea is to reuse blocks of logic instead of creating them manually over and over again. Instead of placing every transistor and wire, the designer places logic blocks in the layout that corresponds to the desired function. The good thing with semi-custom layout is that the required time is decreased and it is far less advanced compared to full custom layout. The downside is that the possibility to optimize the given gates is very limited, so the designer loses some control of the layout. A combination of full and semi-custom layout can often be a good approach, where the logical gates are created manually and optimized and then used in a semi-custom layout instead of using gates created by a supplier. 

iii)Automatic Design:

When a CAD tool creates the layouts automatically and uses standard library cells to realize the circuit. The design is described in high-level hardware description languages such as verilog or VHDL. Then, the high level description is fed to the tool to create the corresponding layout. The CAD tools are able to optimize the generated layouts to meet the desired constraints.. Although the design tools can be told to optimize the generated layout in certain ways, there is just no way for the designer to control exactly how it is generated. Automatic design therefore suffers from creating less optimized layouts compared to full custom design and even semi-custom design. However, automatic design is a very useful tool when the design to be created does not have very strict requirements and when the time to market is more important than a fully optimized design. As mentioned, the automatic design process uses standard cell libraries created by some supplier, generally the one that has supplied the technology that is being used. While these standard cell libraries are quite flexible they may not fit the requirements. A solution to this would be to create a standard cell library manually and use that in the automatic design. This would give the designer total control of the cells in the library and still make it possible to use automatic design tools when creating layouts, thus allowing both the optimization of the design building blocks and rapid layout creation. 

Thanks for reading this entire series may be 2-3 articles so stay tuned with me.

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