Internally Generated Clocks & Gated Clocks Modelling Using Verilog HDL

 Hello Dear Readers,

Today, I will explain how one can modeling an Internally and Gated clock using Verilog HDL.

1). Internally Generated Clocks:

Internally generated clock signals use a system or master clock and generate output as an internally generated clock signal. But, internally generated clock signals need to be avoided as it causes the functional and timing issues in the design. The functional and timing problems are due to the combinational logic propagation delays. The internally generated clock signals can generate a glitch or spike in the output. This can trigger the sequential logic multiple times or can generate undesired output. Even due to violation of setup or hold time these types of designs have timing violations. It is always recommended to generate the internal clocks by using register output logic. But still due to the propagation delay of the flip-flop, the overall cumulative delay or skew can generate glitches or spikes in the design. As shown below, Verilog RTL is described to generate the internal clocks. The generated internal clock signal is used by some other sequential procedural block. 

Verilog Code:

module internal_clock(in_1,in_2,clk,out);

input in_1,in_2,clk;

output reg out;

reg int_clk;

always@(posedge clk)

begin

int_clk<=in_1;

end

always@(posedge int_clk)

begin

out<=in_2;

end

endmodule

The synthesized logic is shown in Fig.1 and the first register is driven by clock ‘clk’ and the second register clock is driven by ‘int_clk’.

Fig.1

2). Gated Clocks:

Gated clock signals are used to enable switching at the clock input and can be used in single or multiple clock domain designs by using the enable inputs. When enable input is high the clock domain is on and when to enable input is low the clock domain is off. The clock gating logic is required to control the clock turn on or turn off. Clock gating is an efficient technique used in ASIC design to reduce the switching power at the clock input of the register. By using the clock gating structure, the clock switching can be stopped as and when required according to the design functional requirements. But the issue with the clock gating is it cannot be used in synchronous designs the reason being it introduces a significant amount of clock skew and even this technique introduces glitches. To avoid the glitches, special care needs to be taken by the ASIC design engineer. Verilog RTL is described below and uses enable input to control the clock switching activity. For ‘enable=1,’ the clock input ‘clk’ toggles, and for ‘enable=0’ clock input is permanently active low so no switching at the clock input. The synthesized logic is shown in Fig.2 where the clock is gated by using AND logic. 

Verilog Code:

module gated_clock(in_1,enable,clk,out);

input in_1,enable,clk;

output reg out;

wire clk_gated;

assign clk_gated=clk&&enable;

always@(posedge clk_gated)

begin

out<=in_1;

end

endmodule

Fig.2

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