Verilog Code of 4bit BCD Adder Using Full Adder

 Hello Dear Readers,

Today in this post I will be providing you a complete Verilog code of 4 Bit BCD Adder using the Full Adder instant model. So before the start, the code keep in mind the algorithms for the BCD adder is if the additional sum is greater than 9 will become up then we add 6 on it to make a valid BCD number so here in my code I have used this algorithm so keep in mind.

Verilog Code:

module bcd_4bit(input [3:0] x,y,input cy_in,output [3:0] sum,output carry,output [4:0] bcd_sum);

add4 a1 (carry,sum,x,y,cy_in);

assign bcd_sum=carry==1?{carry,(sum+4'b0110)}:sum;

endmodule

module add4(cy4,sum,x,y,cy_in

    );

input [3:0] x,y;

input cy_in;

output [3:0] sum;

output cy4;

wire [2:0] carry_out;

add b0(carry_out[0],sum[0],x[0],y[0],cy_in);

add b1(carry_out[1],sum[1],x[1],y[1],carry_out[0]);

add b2(carry_out[2],sum[2],x[2],y[2],carry_out[1]);

add b3(cy4,sum[3],x[3],y[3],carry_out[2]);

endmodule

module add(carry_out,sum,a,b,cy_in

    );

input a,b,cy_in;

output carry_out,sum;

sum s1(sum,a,b,cy_in);

carry c1(carry_out,a,b,cy_in);

endmodule

module sum(sum,a,b,cy_in

    );

input a,b,cy_in;

output sum;

wire t1;

xor g1(t,a,b);

xor g2(sum,t,cy_in);

endmodule

module carry(cy4,a,b,cy_in

    );

input a,b,cy_in;

output cy4;

wire w1,w2,w3;

and g3(w1,a,b);

and g4(w2,b,cy_in);

and g5(w3,a,cy_in);

or g6(cy4,w1,w2,w3);

endmodule

Simulational Results:

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