Skip to main content

YAML in Semiconductor EDA: From Configuration Language to Reusable Design-Flow Methodology

Hello Dear Readers,   Today in this post, I will provide some deep insight about yaml langauge for CAD flow developments with detailed examples. YAML is not a programming language in the same sense as Python, Tcl, C++, or Verilog. It is primarily a human-readable data serialization/configuration language . In semiconductor EDA, that distinction is important because YAML generally describes what a flow should do , while Python/Tcl/Shell and the EDA tools execute the flow . The official YAML specification describes it as a data serialization language designed to be human-friendly and portable across programming languages. For the semiconductor angle, this becomes particularly interesting because YAML can act as a configuration layer between design methodology and EDA implementation . Frameworks such as Hammer explicitly use YAML/JSON configuration and an intermediate representation to standardize information exchanged between design, technology, and tool plugins. 1. Introduction M...
1 comment

Designing of the 4 Tap FIR Filter Using Verilog HDL

 Hello Dear Readers,

Here I have designed a 4 tap FIR filter using Verilog languages and some parts of the Python language to just print the input and output samples that are generating Verilog HDL.
So Let's see the Code of the complete system.
So first of all FIR filter is a system which transfer function has a finite number of impulsive points corresponding to the type of the filters such as high pass, low pass, bandpass, etc... so it has generally two types of structure as shown in the below,


FIR Filter Structures:



Here I have used the first structure in which first multiply input samples with impulse responses so without delay products is available now we give delays to that data means here we have implemented shifted adder for MAC operation of the digital filter.


Verilog Code:

module fir_4tap(input Clk,input signed [7:0] Xin,output reg signed [15:0] Yout);    
//Internal variables.
wire signed   [7:0] H0,H1,H2,H3;
wire signed   [15:0] MCM_block0,MCM_block1,MCM_block2,MCM_block3,shift_add_out1,shift_add_out2,shift_add_out3,Q1,Q2,Q3;    
//filter coefficient initializations.
//h(n) = [-1 -2 5 -1].
    assign H0 = -1;
    assign H1 = -2;
    assign H2 = 5;
    assign H3 = -1;
//Multiple constant multiplications.
    assign MCM_block3 = H3*Xin;
    assign MCM_block2 = H2*Xin;
    assign MCM_block1 = H1*Xin;
    assign MCM_block0 = H0*Xin;
//adders
    assign shift_add_out1 = Q1 + MCM_block2;
    assign shift_add_out2 = Q2 + MCM_block1;
   assign shift_add_out3 = Q3 + MCM_block0;    
//flipflop instantiations (for introducing a delay).
    DFF dff1 (.Clk(Clk),.D(MCM_block3),.Q(Q1));
    DFF dff2 (.Clk(Clk),.D(shift_add_out1),.Q(Q2));
    DFF dff3 (.Clk(Clk),.D(shift_add_out2),.Q(Q3));
//Assign the last adder output to final output.
    always@ (posedge Clk)
        Yout <= shift_add_out3;
endmodule
module DFF(input Clk,input [15:0] D,output reg [15:0] Q);
    
    always@ (posedge Clk)
        Q = D;
    
endmodule
 

module test_bench;

    // Inputs
    reg Clk;
    reg signed [7:0] Xin ;

    // Outputs
    wire signed [15:0] Yout;
integer outfile1,outfile2;

    // Instantiate the Unit Under Test (UUT)
    fir_4tap uut (
        .Clk(Clk), 
        .Xin(Xin), 
        .Yout(Yout)
    );
    
    //Generate a clock with 10 ns clock period.
    initial Clk = 0;
    always 
#5 Clk =~Clk;
 
//Initialize and apply the inputs.
    initial begin
          Xin =0;  #40;
  outfile1=$fopen("output.txt","w");
           outfile2=$fopen("input.txt","w");
$fwrite(outfile1,"%d\n",Xin);  //write as decimal
$fwrite(outfile2,"%d\n",Yout);  //write as decimal
          Xin =0.5; #10;
$fwrite(outfile1,"%d\n",Xin);  //write as decimal
$fwrite(outfile2,"%d\n",Yout);  //write as decimal
          Xin =1;  #10;
$fwrite(outfile1,"%d\n",Xin);  //write as decimal
$fwrite(outfile2,"%d\n",Yout);  //write as decimal 
          Xin =1.5;  #10;
$fwrite(outfile1,"%d\n",Xin);  //write as decimal
$fwrite(outfile2,"%d\n",Yout);  //write as decimal 
          Xin =2; #10;
$fwrite(outfile1,"%d\n",Xin);  //write as decimal
$fwrite(outfile2,"%d\n",Yout);  //write as decimal
          Xin =1.6; #10;
$fwrite(outfile1,"%d\n",Xin);  //write as decimal
$fwrite(outfile2,"%d\n",Yout);  //write as decimal
          Xin =0.8;  #10;
$fwrite(outfile1,"%d\n",Xin);  //write as decimal
$fwrite(outfile2,"%d\n",Yout);  //write as decimal
          Xin =0.5; #10;
$fwrite(outfile1,"%d\n",Xin);  //write as decimal
$fwrite(outfile2,"%d\n",Yout);  //write as decimal
          Xin =0;  #10;
$fwrite(outfile1,"%d\n",Xin);  //write as decimal
$fwrite(outfile2,"%d\n",Yout);  //write as decimal
          Xin =-0.5;  #10;
$fwrite(outfile1,"%d\n",Xin);  //write as decimal
$fwrite(outfile2,"%d\n",Yout);  //write as decimal
Xin =-1;  #10;
$fwrite(outfile1,"%d\n",Xin);  //write as decimal
$fwrite(outfile2,"%d\n",Yout);  //write as decimal
Xin =-1.2;  #10;
$fwrite(outfile1,"%d\n",Xin);  //write as decimal
$fwrite(outfile2,"%d\n",Yout);  //write as decimal
Xin =-2;  #10;
$fwrite(outfile1,"%d\n",Xin);  //write as decimal
$fwrite(outfile2,"%d\n",Yout);  //write as decimal
Xin =-1.7;  #10;
$fwrite(outfile1,"%d\n",Xin);  //write as decimal
$fwrite(outfile2,"%d\n",Yout);  //write as decimal
Xin =-1.2;  #10;
$fwrite(outfile1,"%d\n",Xin);  //write as decimal
$fwrite(outfile2,"%d\n",Yout);  //write as decimal
Xin =-0.8;  #10;
$fwrite(outfile1,"%d\n",Xin);  //write as decimal
$fwrite(outfile2,"%d\n",Yout);  //write as decimal
Xin =-0.4;  #10;
$fwrite(outfile1,"%d\n",Xin);  //write as decimal
$fwrite(outfile2,"%d\n",Yout);  //write as decimal
Xin =0;  #10;
$fwrite(outfile1,"%d\n",Xin);  //write as decimal
$fwrite(outfile2,"%d\n",Yout);  //write as decimal
$fclose(outfile1);
        $fclose(outfile2);
    end    
endmodule


Simulational Results:



Summary of the Obtained Timing Specification:
Timing Specification:

     1.Minimum period: 3.644ns (Maximum   Frequency: 274.424MHz)

     2. Minimum input arrival time before clock: 9.081ns (Setup Time)

    3. Maximum output required time after clock: 4.040ns (Hold Time)





Labels:

Comments

  1. Anonymous27 February 2021 at 05:48

    Great post you are first person who is this much technically writing blogging keep it up.

    ReplyDelete
  2. Anonymous28 February 2021 at 19:12

    what a post brother thanks for posting i have try it and change according to my requirement.

    ReplyDelete
  3. Anonymous1 March 2021 at 16:00

    It is in complete level of the data path means RTL Verilog code right? what we do for the gate level code.

    ReplyDelete
    Replies
    1. ELECTRONICS AND COMMUNICATION HUBS23 March 2021 at 20:48

      So you need to design adder and multiplier at gate level and then instant them in your main code where addition and multiplication is required.

      Delete

Post a Comment

Popular posts from this blog

Signal Electromigration (Signal EM): Violations, Examples, and Practical Fixes

  Hello Dear Readers,   Today in this post, I will provide some deep insight into the Signal Electromigration (Signal EM): Violations, Examples, and Practical Fixes. 1. Introduction: As technology nodes shrink into the deep‑submicron and nanometer regime (7nm, 5nm, 3nm and beyond), electromigration (EM) has become a first‑order reliability concern—not only for power/ground (PG) networks but also for signal nets. Signal EM failures are often underestimated because signal currents are transient and bidirectional. However, with higher switching activity, tighter metal pitches, thinner wires, and aggressive timing closure, signal EM can cause latent or early‑life failures if not addressed properly. This article explains: What Signal EM is and how it differs from PG EM Typical Signal EM violation scenarios Detailed, practical examples Root causes behind each violation Proven solutions and best practices to fix and prevent Signal EM issues 2. What is Signal Electromigration: El...
Post a Comment
Read more

Exploring the Role of LEF Files in VLSI Chip Design: A Beginner's Guide

Hello Dear Readers,   Today in this post, I will provide some deep insight into the LEF file role during the VLSI Chip Design process. In VLSI (Very Large Scale Integration) design, a LEF file is a file that contains information about the physical geometry of the standard cells used in a circuit. LEF stands for Library Exchange Format. A standard cell is a pre-designed logic cell that contains a specific function, such as a flip-flop or an AND gate. Standard cells are designed to be easily combinable and scalable to create more complex circuits. The physical geometry of each standard cell is defined in the LEF file. The LEF file contains information such as the width, height, and position of the pins and metal layers of each standard cell. It also contains information about the physical design rules that govern the placement of these cells on the chip. LEF files are important in VLSI design because they enable the interoperability of different design tools from different vend...
4 comments
Read more

Power Analysis in the VLSI Chip Design

  Hello Dear Readers,   Today in this series of posts I will provide some deep insight into Power Analysis in the VLSI Chip Design. The power analysis flow calculates (estimates of) the active and static leakage power dissipation of the SoC design. This electrical analysis step utilizes the detailed extraction model of the block and global SoC layouts. The active power estimates depend on the availability of switching factors for all signals in the cell netlist. Representative simulation test cases are applied to the netlist model, and the signal value change data are recorded. The output data from the power analysis flow guide the following SoC tape out release assessments:  Total SoC power specification (average and standby leakage): The specification for SoC power is critical for package selection and is used by end customers for thermal analysis of the product enclosure. In addition to the package technology selection, the SoC power dissipation is used to ev...
5 comments
Read more