Hello Dear Readers,   Currently at SiFive  vacancy for ASIC Verification Engineer role . As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits. Job Description:   Requirement: ​ 1-4 years of experience in DV preferably in CPU verification. Proficiency in System Verilog and UVM methodology. Very good object oriented programming skills. Any CPU architecture knowledge (x86, ARM or RISC-V) with test-writing/test plan implementation experience. Any scripting k

Hello Dear Readers,   Currently at Nvidia  vacancy for ASIC Verification Engineer role . NVIDIA is seeking passionate, highly motivated, and creative ASIC Verification Engineers to be part of its Graphics team working on the design of state of the art memory subsystem components used in their industry-leading Graphics Processors and Tegra SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have created a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. In this position, you will be expected to plan and implement IP/Cluster/SOC functional verification of designs that constitute our Graphics Processors and Tegra SOCs. You would work on creating regression plans for code as well as functi

  Hello Dear Readers, At Texas Instruments Bangalore, there is a vacancy for the Physical Design Engineer role. The Radar and Analytics group at Texas Instruments India is looking for passionate Physical Design Engineer to work on next-gen CMOS single-chip millimeter wave sensor portfolio for Automotive Radar and Industrial applications. Physical Design team here owns Complete SoC Synthesis to Layout closure including constraints development and STA & is responsible for design handoff to manufacturing. Physical Design team at Radar & Analytics also works closely with systems and designs team for PPA optimization and has good knowledge of system aspects of the device usage.   Responsibilities: As a Physical Design Engineer in the team, you will be working independently on the entire flow from RTL to GDSII . Understand the design, clock architecture, reset architecture, DFT architecture and influence them as per Physical Design needs. Responsible for Place & Route, Reliab

  Hello Dear Readers,   Currently at Sintegra Inc.  vacancy for Physical Design Engineer PEX role. As a Parasitic Extraction Engineer at Sintegra, you will be responsible for developing, maintaining, and qualifying our sign-off extraction flows and methodologies. You will work with industry-standard extraction tools, ensuring the accuracy and efficiency of our IC designs through meticulous parasitic extraction and correlation processes. Key Responsibilities: Develop, maintain, and qualify sign-off extraction flows and methodologies to ensure accurate parasitic extraction. Utilize industry-standard extraction tools such as Synopsys StarRC and Cadence Quantus QRC to perform detailed parasitic extraction. Perform SPEF (Standard Parasitic Exchange Format) correlation and hierarchical extraction to validate extraction accuracy and optimize extraction flows. Collaborate with design teams to integrate extraction methodologies into the overall IC design flow. Write and maintain scripts in