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VLSI Packaging Evolution and Innovations

Hello Dear Readers,   Today in this post, I will provide some deep insight into the VLSI packaging evolution and innovations. Semiconductor packaging has evolved from a simple protective housing into a critical performance enabler. In the modern VLSI landscape, packaging is no longer an afterthought; it is a fundamental determinant of PPA (Power, Performance, and Area) metrics, often dictating the thermal limits and signal integrity of the final SoC. 1. Traditional Packaging Technologies: These methods are the workhorses of the industry, widely used for low-to-medium complexity devices where cost-efficiency is paramount. Wire Bonding (QFN, QFP, DIP): Wire bonding is the most mature interconnection technology. It uses thin gold, copper, or aluminum wires to connect the die's bond pads to the package's internal leadframe. Implementation: The die is attached face-up to a leadframe or substrate. A wire bonder uses thermocompression or ultrasonic energy to attach wires betwee...
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ASIC Verification Engineer at Nvidia

Hello Dear Readers, 

Currently at Nvidia vacancy for ASIC Verification Engineer role.

NVIDIA is seeking passionate, highly motivated, and creative ASIC Verification Engineers to be part of its Graphics team working on the design of state of the art memory subsystem components used in their industry-leading Graphics Processors and Tegra SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have created a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.

In this position, you will be expected to plan and implement IP/Cluster/SOC functional verification of designs that constitute our Graphics Processors and Tegra SOCs. You would work on creating regression plans for code as well as functional coverage closure. You would perform pre-silicon validation activities such as XPROP simulations and GLS.

What you’ll be doing:

  • Own ASIC verification of IP/Cluster for complicated designs in RTL.

  • Work with HW architects and designers to make the right implementation choices.

  • Interact with the Performance verification teams to augment verification through dynamic simulations and/or Formal verification techniques.

  • You will work with the specifications and ensure functional and code coverage of all the RTL which you will verify.

  • Partner with and enable FPGA and S/W teams to ensure that S/W is tested.

  • Be involved with post-silicon verification and debug.

What we need to see:

  • BS / MS or equivalent experience.

  • 2+ years of design experience.

  • Experience in ASIC verification of complex design units for at least one or two projects.

  • Background with design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB).

  • Exposure to System Verilog and UVM based methodology for ASIC verification is highly desired.

Ways to stand out from the crowd:

  • Knowledge of Memory controllers or prior experience with verification of IP/clusters involving access to Memory.

  • Good debugging and problem solving skills.

  • Scripting knowledge (Python/Perl/shell).

  • Good interpersonal skills and ability & desire to work as a part of a team.





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