Skip to main content

RTL Design Engineer at Skyroot Aerospace

Hello, Dear Readers, Skyroot Aerospace has a vacancy for the RTL Design Engineer role. About Skyroot Aerospace: A cutting-edge startup founded by ex-ISRO scientists. Dedicated to affordable space access, we're rewriting aerospace technology rules. Our dynamic team fosters inventiveness, collaboration, and relentless excellence. Join us on a transformative journey to redefine space possibilities. Welcome to the forefront of space innovation with Skyroot Aerospace! Purpose of role: Understand architectural requirements and Design micro-architecture, implement design blocks using VHDL/Verilog for FPGA based Avionics packages for orbital launch vehicles and ground infrastructure. Job Requirements: 2+ Years of RTL and system design experience. Strong knowledge on Digital System Design (DSD). Strong knowledge of RTL/SoC design/integration with VHDL/Verilog. Strong knowledge in problem solving and debugging skills. Ability to understand architectural requirements and Design micro-archite...
Post a Comment

ASIC Verification Engineer at Nvidia

Hello Dear Readers, 

Currently at Nvidia vacancy for ASIC Verification Engineer role.

NVIDIA is seeking passionate, highly motivated, and creative ASIC Verification Engineers to be part of its Graphics team working on the design of state of the art memory subsystem components used in their industry-leading Graphics Processors and Tegra SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have created a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.

In this position, you will be expected to plan and implement IP/Cluster/SOC functional verification of designs that constitute our Graphics Processors and Tegra SOCs. You would work on creating regression plans for code as well as functional coverage closure. You would perform pre-silicon validation activities such as XPROP simulations and GLS.

What you’ll be doing:

  • Own ASIC verification of IP/Cluster for complicated designs in RTL.

  • Work with HW architects and designers to make the right implementation choices.

  • Interact with the Performance verification teams to augment verification through dynamic simulations and/or Formal verification techniques.

  • You will work with the specifications and ensure functional and code coverage of all the RTL which you will verify.

  • Partner with and enable FPGA and S/W teams to ensure that S/W is tested.

  • Be involved with post-silicon verification and debug.

What we need to see:

  • BS / MS or equivalent experience.

  • 2+ years of design experience.

  • Experience in ASIC verification of complex design units for at least one or two projects.

  • Background with design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB).

  • Exposure to System Verilog and UVM based methodology for ASIC verification is highly desired.

Ways to stand out from the crowd:

  • Knowledge of Memory controllers or prior experience with verification of IP/clusters involving access to Memory.

  • Good debugging and problem solving skills.

  • Scripting knowledge (Python/Perl/shell).

  • Good interpersonal skills and ability & desire to work as a part of a team.





Comments

Post a Comment

Popular posts from this blog

Exploring the Role of LEF Files in VLSI Chip Design: A Beginner's Guide

Hello Dear Readers,   Today in this post, I will provide some deep insight into the LEF file role during the VLSI Chip Design process. In VLSI (Very Large Scale Integration) design, a LEF file is a file that contains information about the physical geometry of the standard cells used in a circuit. LEF stands for Library Exchange Format. A standard cell is a pre-designed logic cell that contains a specific function, such as a flip-flop or an AND gate. Standard cells are designed to be easily combinable and scalable to create more complex circuits. The physical geometry of each standard cell is defined in the LEF file. The LEF file contains information such as the width, height, and position of the pins and metal layers of each standard cell. It also contains information about the physical design rules that govern the placement of these cells on the chip. LEF files are important in VLSI design because they enable the interoperability of different design tools from different vend...
4 comments
Read more

Internship - SoC /IP Design at NXP India

Hello Dear Readers, Currently, at NXP India  vacancy for  Internship - SoC /IP Design   role.   We are looking for a Master degree student with Electronics and Communication Engineering, or related field, with an emphasis on SoC design. This is a full-time internship with a duration of about 11-12 months. Job Responsibility: Working with our experienced design team to design state of the art SoC hardware specific segment applications like Automotive, IoT, voice/object recognition, security, smart connectivity and touch sensing . Assisting experienced engineers with End-to-end ownership of SoC Design, Verification and implementation (Physical Design). Design and verify digital and Mixed-signal IPs. Document designs and present results. Job Qualification: Master student in electronic/computer engineering Creative and positive mindset Good knowledge on CMOS technologies Great communication skills, interpersonal skills, teamwork skills and can-do attitude Desire for a ca...
Post a Comment
Read more

IC Design Engineer at Broadcom

  Hello Dear Readers, Currently, at Broadcom vacancy for an IC Design Engineer role. Job Description: Candidate would be required to work on various phases of SOC physical design activities. The job will include but not limited to block level – floor-planning, partitioning, placement, clock tree synthesis, route, physical verification (LVS/DRC/ERC/Antenna etc). Should be able to meet congestion, timing and area metrics.  Candidate would be required to do equivalence checks, STA, Crosstalk delay analysis, noise analysis, power optimization. Should be able to implement timing and functional ECOs. Should have excellent problem-solving skill to help through congestion resolution and timing closure. Should have experience formal verification and timing analysis and ECO implementation. Experience with tools such as Innovus/Encounter, ICC, Caliber, LEC, Primetime etc is highly desirable. Candidate should be able to work independently and guide other team members. Should be ...
Post a Comment
Read more