Hello Dear Readers, Currently at Cadence Noida vacancy for the intern-WFO role. Educational Qualifications : BE/B.Tech Or ME/M.Tech Tenure: 11 months Responsibilities: Interns at Cadence play a crucial role in bringing new creative ideas to Cadence and helping us in our pursuit to solve cutting-edge technical challenges. Interns are part of project teams and are expected to learn the respective tools, flow & associated technologies on the job. The interns are assigned a mentor/manager who continually helps and guides them during this learning process. During this training, the interns get an opportunity to work on multiple live assignments to learn the workings of the actual tool. They also get to learn the nuances of working in a team and the corporate world. From the first day at Cadence, the interns are expected to develop high performance capabilities. They are encouraged and supported to take charge of their learning and leverage this opportunity fully to le...

  Hello Dear Readers,   Today here below I have collected practice questions that are more frequently asked by the interviewer. Q-1: What are the various options used by the synthesis tool to optimize the circuit to meet timing? Q-2: If we do synthesis of an RTL using 2 SDCs, one at 100MHz and the other one at 200MHz, which netlist will look bigger? Q-3:  If we do synthesis of an RTL using 2 LIBs, one at 45nm technology and the other one at 28nm technology, which netlist will look bigger? Q-4: How does synthesis tool compute the cell delays without knowing load capacitance? Q-5: What happens to clock nets during synthesis? Q-6: Can clock gating be done during synthesis? Q-7: What happens to power and ground nets during synthesis? Q-8: How memories and hard IPs are handled during synthesis? Q-9: Which steps of the verification method need test vectors? Q-10: After synthesis, if we find a bug in RTL, how do we fix it in the netlist? Q-11: Will flip flop instance names be th...

  Hello Dear Readers,   Today in this post I will provide some techniques for timing optimization in ASIC Design. Timing Optimization Techniques are as follows: 1. Mapping: Mapping converts primitive logic cells found in a netlist to technology-specific logic gates found in the library on the timing critical paths. 2. Unmapping: Unmapping converts the technology-specific logic gates in the netlist to primitive logic gates on the timing critical paths. 3. Pin Swapping : Pin swapping optimization examines the slacks on the inputs of the gates on the worst timing paths and optimizes the timing by swapping nets attached to the input pins, so the net with the least amount of slack is put on the fastest path through the gate without changing the function of the logic. 4. Buffering: Buffers are inserted in the design to drive a load that is too large for a logic cell to efficiently drive. If the net is too long then the net is broken and buffers are inserted to improve the transition...

  Hello Dear Readers,   Today in this post I will provide some basics to advanced ARM's assembly language practice QA part-4, I have used the Keil tool for code writing. Q-1).  Write an assembly language program that performs a mode change by modifying the contents of the CPSR.    a. The mode you should change to is user mode, and you have to modify the mode field of CPSR by the value of 0x10.    b. This assumes that the current mode is a privileged mode such as supervisor mode. Code: ; program which changes the microprocessor mode  masking equ 0x1f  user_mode equ 0x10   area change, code, readonly entry   MRS R0,CPSR; read the status of the microprocessor   BIC R0, R0,#masking; apply the masking bit   ORR R0,R0,#user_mode ; set the mode user_mode   MSR CPSR_C,R0 ; written back with control_field_mask   END  Output: Q-2).  Write an assembly language program that generates S...