Hello Dear Readers, Today in this post, I will provide some deep insight into the VLSI packaging evolution and innovations. Semiconductor packaging has evolved from a simple protective housing into a critical performance enabler. In the modern VLSI landscape, packaging is no longer an afterthought; it is a fundamental determinant of PPA (Power, Performance, and Area) metrics, often dictating the thermal limits and signal integrity of the final SoC. 1. Traditional Packaging Technologies: These methods are the workhorses of the industry, widely used for low-to-medium complexity devices where cost-efficiency is paramount. Wire Bonding (QFN, QFP, DIP): Wire bonding is the most mature interconnection technology. It uses thin gold, copper, or aluminum wires to connect the die's bond pads to the package's internal leadframe. Implementation: The die is attached face-up to a leadframe or substrate. A wire bonder uses thermocompression or ultrasonic energy to attach wires betwee...
Hello Dear Readers,
Currently, at Baya Systems, there is a vacancy for a Physical Design Engineer role.
About the role: We are seeking a seasoned Physical Design Engineer with a strong background in all aspects of Physical Design and Implementation flows. The ideal candidate will play a key role in shaping our technology portfolio, bringing expertise and creativity to our solutions
Responsibilities:
- Own RTL to GDS physical implementation flows for synthesis, floor-planning, place and route, clock tree synthesis, timing & power closure, EM/IR, PDV and final PD sign off
- Own physical design & implementation of high-performance designs from block level to system level components
- Deep collaboration with Micro-architects to explore performance, power and area trade-offs for high performance and low power designs
- Physical implementation feasibility studies and design recommendations for best PPA
- Develop methodologies and recipes for various stages of physical implementation
- Perform various physical design validation (PDV) flows for Timing, Power, EM/IR, etc. to ensure physical design quality
- Perform design rule checking (DRC), (LVS) checks, and other physical verification tasks
Qualifications:
- BS, MS in Electrical Engineering or Computer Engineering or related degree
- Experience in all aspects of physical design including synthesis, floor planning, place & route, timing & power closure, EM/IR, physical design validation, etc
- Experience with synthesis, place & route, static timing analysis and PDV tools
- Experience in implementing clock trees and power grids
- Experience with scripting for physical design flow automation
- Experience with Synopsys Design Compiler, Prime Time, ICC, Fusion Compiler etc.
- Good knowledge of high-performance and low-power microarchitecture and logic design principles
- Understanding of modern (sub 7nm) sub-micron technology nodes and device physics
- Basic knowledge of System/SoC Architecture and System Verilog RTL coding
- Strong communication and collaboration skills
Comments
Post a Comment