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VLSI Packaging Evolution and Innovations

Hello Dear Readers,   Today in this post, I will provide some deep insight into the VLSI packaging evolution and innovations. Semiconductor packaging has evolved from a simple protective housing into a critical performance enabler. In the modern VLSI landscape, packaging is no longer an afterthought; it is a fundamental determinant of PPA (Power, Performance, and Area) metrics, often dictating the thermal limits and signal integrity of the final SoC. 1. Traditional Packaging Technologies: These methods are the workhorses of the industry, widely used for low-to-medium complexity devices where cost-efficiency is paramount. Wire Bonding (QFN, QFP, DIP): Wire bonding is the most mature interconnection technology. It uses thin gold, copper, or aluminum wires to connect the die's bond pads to the package's internal leadframe. Implementation: The die is attached face-up to a leadframe or substrate. A wire bonder uses thermocompression or ultrasonic energy to attach wires betwee...
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Product Engineer - STA at Siemens India

Hello Dear Readers,

Currently, at Siemens EDA (Siemens Digital Industries Software) vacancy for Product Engineer - STA role.

This is your role:

  • Working on 7nm and 5nm designs with various customers for deployment of Aprisa place and route tools.
  • Are you expertised in solving customer's problems for critical designs to achieve desired performance, area and power targets!
  • Responsible to develop flow and methodology for doing placement, CTS and routing. Also, provide training and technical support to customers using Aprisa tools

We don’t need superheroes, just superminds!

  • We are looking for someone with hands on experience in Physical Design (floorplan, placement, CTS and routing) and timing closure of complex blocks and/or Full Chip designs.
  • Hands-on experience with commercial place & route tools like Synopsys-lCC2, Cadence-Innovus or Aprisa is a must.
  • Tapeout experience of 2 or more projects is a must.
  • Do you have good understanding of timing, power and area trade-offs?
  • Ability to pickup new flows, learn on the job and influence QOR is a must.
  • We are looking for an experienced design delivering with multiple voltage islands and top-level floor-planning & chip-assembly is a plus.
  • Strong verbal and written communication skills; good presentation skills; good problem solving and debugging skills.

Education:

  • BE/B.Tech in Electronics and Communication (E&C) or Electrical or Telecom Engineering
  • ME/M.Tech in VLSI or Microelectronics is a plus


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