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Physical Design Methodology Engineer at Texas Instruments

  Hello Dear Readers, Texas Instruments Bangalore has a vacancy for the Physical Design Engineer role. We need an Physical Design Methodology Engineer to join our ATD team. The candidate should have a strong background in back-end design of ASIC/SoC chips. The ideal candidate will have a bachelor’s or master’s degree in Electrical Engineering or a related field. Requirements: 1 - 2 Years of experience in physical design Bachelor’s or master’s degree in Electrical/Electronics Engineering or a related field Strong understanding of physical design principles Must know the basics of floorplan, placement, CTS, routing, ECO, Physical Verification Proficiency in back-end design tools, such as Cadence Genus/Innovus/Tempus/Voltus Excellent problem-solving skills and attention to detail Effective communication and collaboration skills Responsibilities: Synthesis to GDSII Perform full Physical design flow and its verification Work closely with Digital Design and DFT engineers Ensure...
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Product Engineer - STA at Siemens India

Hello Dear Readers,

Currently, at Siemens EDA (Siemens Digital Industries Software) vacancy for Product Engineer - STA role.

This is your role:

  • Working on 7nm and 5nm designs with various customers for deployment of Aprisa place and route tools.
  • Are you expertised in solving customer's problems for critical designs to achieve desired performance, area and power targets!
  • Responsible to develop flow and methodology for doing placement, CTS and routing. Also, provide training and technical support to customers using Aprisa tools

We don’t need superheroes, just superminds!

  • We are looking for someone with hands on experience in Physical Design (floorplan, placement, CTS and routing) and timing closure of complex blocks and/or Full Chip designs.
  • Hands-on experience with commercial place & route tools like Synopsys-lCC2, Cadence-Innovus or Aprisa is a must.
  • Tapeout experience of 2 or more projects is a must.
  • Do you have good understanding of timing, power and area trade-offs?
  • Ability to pickup new flows, learn on the job and influence QOR is a must.
  • We are looking for an experienced design delivering with multiple voltage islands and top-level floor-planning & chip-assembly is a plus.
  • Strong verbal and written communication skills; good presentation skills; good problem solving and debugging skills.

Education:

  • BE/B.Tech in Electronics and Communication (E&C) or Electrical or Telecom Engineering
  • ME/M.Tech in VLSI or Microelectronics is a plus


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