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Physical Design Methodology Engineer at Texas Instruments

  Hello Dear Readers, Texas Instruments Bangalore has a vacancy for the Physical Design Engineer role. We need an Physical Design Methodology Engineer to join our ATD team. The candidate should have a strong background in back-end design of ASIC/SoC chips. The ideal candidate will have a bachelor’s or master’s degree in Electrical Engineering or a related field. Requirements: 1 - 2 Years of experience in physical design Bachelor’s or master’s degree in Electrical/Electronics Engineering or a related field Strong understanding of physical design principles Must know the basics of floorplan, placement, CTS, routing, ECO, Physical Verification Proficiency in back-end design tools, such as Cadence Genus/Innovus/Tempus/Voltus Excellent problem-solving skills and attention to detail Effective communication and collaboration skills Responsibilities: Synthesis to GDSII Perform full Physical design flow and its verification Work closely with Digital Design and DFT engineers Ensure...
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Engineer I-CAD at Silicon Labs

  Hello Dear Readers,

Currently, at Silicon Labs Hyderabad vacancy for Engineer I-CAD role. 

As a senior member of our CAD team, you will determine, develop and support infrastructure needs and design flows for our rapidly growing IoT product division. This is a high visibility role, which requires fluid interaction with Silicon Labs’ CAD, DevOps, IT, IP, PDK, PV and Design teams. The candidate should have an excellent grasp of design data management practices, EDA tools, LSF, and diverse processes & platforms for deep submicron design and compute environments for chip design for modern hardware systems. Proven experience working on design and compute environments will be greatly preferred for this role.

Proven experience working across a range of process nodes from smaller geometries (22nm and below) to high voltage processes (0.5u) is critical for the role.

Key Qualifications:

  • Ideal candidate should have 3+ years of experience in chip design CAD with exposure to EDA tools from multiple vendors like Mentor, Cadence and Synopsys
  • Strong programming skills in Python is a must for this role
  • Programming experience in Perl, Tcl and Shell scripting experience would be desirable
  • Sound knowledge of design flow from RTL to GDS
  • Experience in using and administering FlexLM, IBM LSF
  • Knowledge of  advanced usage of data management and version control tools like Perforce, Subversion, Cliosoft SOS, Methodics IPLM
  • Knowledge of  EDA tool installation, access control mechanisms in multi-site Linux-based Secure Design Environments
  • Experience with Cadence Virtuoso tools, Mentor Calibre will be definite plus
  • Ability to work independently, drive decision-making, strong communication, and documentation skills are critical
  • Familiarity with Analog and Digital design engineering concepts
  • Excellent documentation and communication skills. Familiarity with Jira and Confluence is a plus



 

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