Skip to main content

Silicon Engineering Intern at Microsoft India

  Hello Dear Readers, Currently, at Microsoft India  vacancy for Silicon Engineering Intern role. At Microsoft, Interns work on real-world projects in collaboration with teams across the world, while having fun along the way. You’ll be empowered to build community, explore your passions and achieve your goals. This is your chance to bring your solutions and ideas to life while working on cutting-edge technology. Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond. Qualifications: Currently pursuing a bachelor’s degree in Electronics Engineering, Electrical & Electronics/Computer Science Engineering.   Preferred Qualifications (PQs):   Experience or classes in t
Post a Comment

Physical Design Engineer at SierraEdge AI

 Hello Dear Readers, 

Currently at SierraEdge AI vacancy for Physical Design Engineer role.

SierraEdge AI is a semiconductor and AI services startup based in Bengaluru. Our team consists of young, enthusiastic, and passionate engineers who are dedicated to problem-solving. We specialize in the VLSI domain and aim to provide high-end services to key accounts while nurturing emerging engineering talent with innovative value.

Role Description:
This is a full-time on-site role for a Physical Design Engineer at SierraEdge AI in Bengaluru. The Physical Design Engineer will be responsible for tasks such as physical design, physical verification, logic design, circuit design, and RTL design on a day-to-day basis.

Qualifications:

  • Physical Design, Physical Verification, and Logic Design skills
  • Circuit Design and RTL Design skills
  • Experience in semiconductor industry
  • Knowledge of EDA tools and methodologies
  • Strong problem-solving skills
  • Bachelor's degree in Electrical Engineering or related field
  • Excellent teamwork and communication skills



Comments

Post a Comment

Popular posts from this blog

SDC (Synopsys Design Constraints) contents part 4

Today, we will be discussing the remaining constraints mentioned in the SDC, which pertain to timing exceptions and design rules. This is the final part of the SDC contents. This is going to be interesting, especially with multicycle paths. Take time to read and try to comprehend. 10. set_max_transition     By setting max transition value, our design checks that all ports and pins are meeting the specified limits mentioned in SDC. If these are not satisfied then timing report will give DRVs (design rule violations) in terms of slack. This is specified as               set_max_transition 0.5  UBUF1/A setting maximum limit of 500ps on pin A of Buffer1. 11. set_max_capacitance     This is same as max transition, setting the maximum capacitance value. if our design not meeting this value then violation will occur. This will also reports under design rule violations in terms of slack.     set_max_capacitance 0.7 [all_nets] setting maximum capacitance of 700fF on all nets. similarly, set_max
1 comment
Read more

Apprenticeship CAI at MediaTek Bangalore

Hello Dear Readers,   Currently at MediaTek Bangalore vacancy for an Apprenticeship CAI role. Job Description: B.Tech degree in Electrical/Electronics Engineering with a strong educational background in Digital circuit design Experience in physical design of high performance design with frequencies > 2 Ghz. Experienced in hierarchical design, budgeting, multiple voltage domains and multiple clock domains. Strong skills with Cadence Encounter. Solid understanding of STA and timing constraints. Experienced in working on advanced process nodes (16nm). Strong expertise in Physical Verification to debug LVS/DRC issues at the block level. Requirement: B.Tech degree in Electrical/Electronics Engineering with strong educational background in Digital circuit design Experience in physical design of high performance design with frequencies > 2 Ghz. Experienced in hierarchical design, budgeting, multiple voltage domains and multiple clock domains. Strong skills with Cadence Encounter. Solid
Post a Comment
Read more

IC Physical Design (PnR) at Ulkasemi

Hello Dear Readers,   Ulkasemi  has a vacancy for an IC Physical Design (PnR) role. Job Overview: As a full-time Trainee Engineer, the individual will be working on IC Physical Design implementation from RTL to GDSII to create design databases ready for manufacturing with a special focus on power, performance & area optimization with next-generation state-of-the-art process technologies. Job Responsibilities: Perform physical design implementation which includes Floor planning, Power Planning, Clock Tree Synthesis, Place and Route, ECO, Logic Equivalence checks Timing analysis, physical & electrical verification, driving the sign-off closure meeting schedule, and design goals Develop flow, methodologies, and automation scripts for various implementation steps Follow the instructions, compile documents, prepare deliverables, and report to the team lead Should remain up to date with the latest technology trends Educational Qualification:   B.Sc/M.Sc   in EEE or equivalent degree
Post a Comment
Read more