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VLSI Packaging Evolution and Innovations

Hello Dear Readers,   Today in this post, I will provide some deep insight into the VLSI packaging evolution and innovations. Semiconductor packaging has evolved from a simple protective housing into a critical performance enabler. In the modern VLSI landscape, packaging is no longer an afterthought; it is a fundamental determinant of PPA (Power, Performance, and Area) metrics, often dictating the thermal limits and signal integrity of the final SoC. 1. Traditional Packaging Technologies: These methods are the workhorses of the industry, widely used for low-to-medium complexity devices where cost-efficiency is paramount. Wire Bonding (QFN, QFP, DIP): Wire bonding is the most mature interconnection technology. It uses thin gold, copper, or aluminum wires to connect the die's bond pads to the package's internal leadframe. Implementation: The die is attached face-up to a leadframe or substrate. A wire bonder uses thermocompression or ultrasonic energy to attach wires betwee...
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PDCAD Engineer at SiFive

Hello Dear Readers, 

Currently at SiFive vacancy for PDCAD Engineer role.

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.

Job Description:

 

As a PD CAD Engineer in the Implementation team, you will contribute to the development of industry-leading CPU IP to support the SiFive vision of enabling chip design by anyone. We are looking for people who are as excited as we are about working in a fast-paced dynamic environment to bring new hardware IP to market quickly, with high quality and exceptional performance.

Responsibilities:

  • Developing and supporting the physical design implementation and signoff flows

  • Developing and maintaining custom CAD tools for implementation and signoff

  • Developing infrastructure for design audits, tracking and analysis, and release

  • Working with vendors to resolve tool issues.

Requirements:

  • Proficiency with scripting languages such as tcl and Python

  • Experience with CAD flow development on latest EDA tools in PnR and signoff

  • Experience in one or more aspects of PD such as synthesis, PnR, timing, physical verification, IR/EM

  • Experience with Version Control Systems and Makefiles is a plus

  • Attention to detail and a focus on high-quality design

  • Ability to work well with others and a belief that engineering is a team sport.

  • Bachelor’s degree in Electrical Engineering or Computer Engineering.

 


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