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Physical Design Methodology Engineer at Texas Instruments

  Hello Dear Readers, Texas Instruments Bangalore has a vacancy for the Physical Design Engineer role. We need an Physical Design Methodology Engineer to join our ATD team. The candidate should have a strong background in back-end design of ASIC/SoC chips. The ideal candidate will have a bachelor’s or master’s degree in Electrical Engineering or a related field. Requirements: 1 - 2 Years of experience in physical design Bachelor’s or master’s degree in Electrical/Electronics Engineering or a related field Strong understanding of physical design principles Must know the basics of floorplan, placement, CTS, routing, ECO, Physical Verification Proficiency in back-end design tools, such as Cadence Genus/Innovus/Tempus/Voltus Excellent problem-solving skills and attention to detail Effective communication and collaboration skills Responsibilities: Synthesis to GDSII Perform full Physical design flow and its verification Work closely with Digital Design and DFT engineers Ensure...
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CPU RTL Power Management Design Engineer at Qualcomm

 Hello Dear Readers,

Currently, at Qualcomm Bangalore vacancy for CPU RTL Power Management Design Engineer role.

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Requirements:

● Performance exploration. Explore high performance strategies working with the CPU modeling team.

● Microarchitecture development and specification. From early high-level architectural exploration, through micro architectural research and arriving at a detailed specification.

● RTL ownership. Development, assessment and refinement of RTL design to target power, performance, area and timing goals.

● Functional verification support. Help the design verification team execute on the functional verification strategy.

● Performance verification support. Help verify that the RTL design meets the performance goals.

● Design delivery. Work with multi-functional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability and power.

● Thorough knowledge of microprocessor architecture including expertise in one or more of the following areas: Active power management (DVFS) , Idle power management , Limit management (TDP, Thermal and Over-current protection), Clock management, Debug and Trace architecture.

● Knowledge of Verilog and/or VHDL. Experience with simulators and waveform debugging tools.

● Knowledge of logic design principles along with timing and power implications.

Minimum Qualifications:

• Associate's degree in computer science, Electrical/Electronic Engineering, Engineering, or related field.

MS degree in Computer or Electrical Engineering.

● Understanding of low power microarchitecture techniques.

● Understanding of high performance techniques and trade-offs in a CPU microarchitecture.

● Experience using a scripting language such as Perl or Python.



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