Skip to main content

Discover New Horizons with CG SEMI Job Opportunity

  Hello, Dear Readers,   Currently at CG SEMI has multiple job vacancies in semiconductors.  Apply Here Connect with me  1.Linkedln 2.Instagram 3.Facebook 4.WhatsApp
Post a Comment

Fresher, ASIC Verification at Kinara Inc.

Hello Dear Readers, 

Currently at Kinara Inc. vacancy for Fresher, ASIC Verification role.

Overview:

They are seeking a talented junior ASIC Verification Engineer to join our dynamic team. The successful candidate will be responsible for leading and executing verification efforts for complex ASIC designs, ensuring the quality and reliability of our products.

Key Responsibilities:

  1. Develop and maintain verification plans, testbenches, and test cases for ASIC designs.
  2. Design and implement SystemVerilog/UVM-based verification environments.
  3. Create and execute test cases to verify functionality, performance, and compliance with specifications.
  4. Write testplans, testcases at unit or SOC level.

Necessary Qualifications:

  1. Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
  2. Expertise in SystemVerilog, C, C++ languages.
  3. Experience with verification tools such as VCS, QuestaSim, or similar is helpful.
  4. Excellent problem-solving and debugging skills.
  5. Strong communication and teamwork abilities.

Preferred Qualifications:

  1. Experience with scripting languages such as Python or Perl .
  2. Programming languages such as C,C++.
  3. Knowledge of industry standards and protocols (e.g., AXI, AHB, etc).
  4. Familiarity with formal verification techniques.

Comments

Post a Comment

Popular posts from this blog

Signal Electromigration (Signal EM): Violations, Examples, and Practical Fixes

  Hello Dear Readers,   Today in this post, I will provide some deep insight into the Signal Electromigration (Signal EM): Violations, Examples, and Practical Fixes. 1. Introduction: As technology nodes shrink into the deep‑submicron and nanometer regime (7nm, 5nm, 3nm and beyond), electromigration (EM) has become a first‑order reliability concern—not only for power/ground (PG) networks but also for signal nets. Signal EM failures are often underestimated because signal currents are transient and bidirectional. However, with higher switching activity, tighter metal pitches, thinner wires, and aggressive timing closure, signal EM can cause latent or early‑life failures if not addressed properly. This article explains: What Signal EM is and how it differs from PG EM Typical Signal EM violation scenarios Detailed, practical examples Root causes behind each violation Proven solutions and best practices to fix and prevent Signal EM issues 2. What is Signal Electromigration: El...
Post a Comment
Read more

Exploring the Role of LEF Files in VLSI Chip Design: A Beginner's Guide

Hello Dear Readers,   Today in this post, I will provide some deep insight into the LEF file role during the VLSI Chip Design process. In VLSI (Very Large Scale Integration) design, a LEF file is a file that contains information about the physical geometry of the standard cells used in a circuit. LEF stands for Library Exchange Format. A standard cell is a pre-designed logic cell that contains a specific function, such as a flip-flop or an AND gate. Standard cells are designed to be easily combinable and scalable to create more complex circuits. The physical geometry of each standard cell is defined in the LEF file. The LEF file contains information such as the width, height, and position of the pins and metal layers of each standard cell. It also contains information about the physical design rules that govern the placement of these cells on the chip. LEF files are important in VLSI design because they enable the interoperability of different design tools from different vend...
4 comments
Read more

Power Analysis in the VLSI Chip Design

  Hello Dear Readers,   Today in this series of posts I will provide some deep insight into Power Analysis in the VLSI Chip Design. The power analysis flow calculates (estimates of) the active and static leakage power dissipation of the SoC design. This electrical analysis step utilizes the detailed extraction model of the block and global SoC layouts. The active power estimates depend on the availability of switching factors for all signals in the cell netlist. Representative simulation test cases are applied to the netlist model, and the signal value change data are recorded. The output data from the power analysis flow guide the following SoC tape out release assessments:  Total SoC power specification (average and standby leakage): The specification for SoC power is critical for package selection and is used by end customers for thermal analysis of the product enclosure. In addition to the package technology selection, the SoC power dissipation is used to ev...
5 comments
Read more