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SRAM/Memory CAD Engineer at Qualcomm

  Hello Dear Readers, Qualcomm Bangalore currently has a vacancy for an SRAM/Memory CAD Engineer. As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems,  Digital/Analog/RF/optical  systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: • Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronic...
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Apprenticeship CAI at MediaTek Bangalore

Hello Dear Readers, 

Currently at MediaTek Bangalore vacancy for an Apprenticeship CAI role.

Job Description:
  • B.Tech degree in Electrical/Electronics Engineering with a strong educational background in Digital circuit design
  • Experience in physical design of high performance design with frequencies > 2 Ghz.
  • Experienced in hierarchical design, budgeting, multiple voltage domains and multiple clock domains.
  • Strong skills with Cadence Encounter.
  • Solid understanding of STA and timing constraints.
  • Experienced in working on advanced process nodes (16nm).
  • Strong expertise in Physical Verification to debug LVS/DRC issues at the block level.

Requirement:
  • B.Tech degree in Electrical/Electronics Engineering with strong educational background in Digital circuit design
  • Experience in physical design of high performance design with frequencies > 2 Ghz.
  • Experienced in hierarchical design, budgeting, multiple voltage domains and multiple clock domains.
  • Strong skills with Cadence Encounter.
  • Solid understanding of STA and timing constraints.
  • Experienced in working on advanced process nodes (16nm).
  • Strong expertise in Physical Verification to debug LVS/DRC issues at block level.  

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