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YAML in Semiconductor EDA: From Configuration Language to Reusable Design-Flow Methodology

Hello Dear Readers,   Today in this post, I will provide some deep insight about yaml langauge for CAD flow developments with detailed examples. YAML is not a programming language in the same sense as Python, Tcl, C++, or Verilog. It is primarily a human-readable data serialization/configuration language . In semiconductor EDA, that distinction is important because YAML generally describes what a flow should do , while Python/Tcl/Shell and the EDA tools execute the flow . The official YAML specification describes it as a data serialization language designed to be human-friendly and portable across programming languages. For the semiconductor angle, this becomes particularly interesting because YAML can act as a configuration layer between design methodology and EDA implementation . Frameworks such as Hammer explicitly use YAML/JSON configuration and an intermediate representation to standardize information exchanged between design, technology, and tool plugins. 1. Introduction M...
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Apprenticeship CAI at MediaTek Bangalore

Hello Dear Readers, 

Currently at MediaTek Bangalore vacancy for an Apprenticeship CAI role.

Job Description:
  • B.Tech degree in Electrical/Electronics Engineering with a strong educational background in Digital circuit design
  • Experience in physical design of high performance design with frequencies > 2 Ghz.
  • Experienced in hierarchical design, budgeting, multiple voltage domains and multiple clock domains.
  • Strong skills with Cadence Encounter.
  • Solid understanding of STA and timing constraints.
  • Experienced in working on advanced process nodes (16nm).
  • Strong expertise in Physical Verification to debug LVS/DRC issues at the block level.

Requirement:
  • B.Tech degree in Electrical/Electronics Engineering with strong educational background in Digital circuit design
  • Experience in physical design of high performance design with frequencies > 2 Ghz.
  • Experienced in hierarchical design, budgeting, multiple voltage domains and multiple clock domains.
  • Strong skills with Cadence Encounter.
  • Solid understanding of STA and timing constraints.
  • Experienced in working on advanced process nodes (16nm).
  • Strong expertise in Physical Verification to debug LVS/DRC issues at block level.  

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