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Verification Engineer or Senior Verification Engineer SOC at MIPS India

Hello Dear Readers, Currently, at MIPS India  vacancy for a Verification Engineer or Senior Verification Engineer SOC role. We are seeking an experienced Verification Engineer or Senior Verification Engineer SOC. This position involves extensive hands-on experience with CPU verification using industry-standard functional verification methodologies, formal verification, and constrained random generators, and reference model-based checkers. The candidate must be able to take critical decisions and completely own verification closure for a block or feature. This position involves cross-functional interaction with CPU designers and architects and working across sites to ensure high-quality CPU designs for customers. You will: Take full ownership and drive verification efforts to closure Work closely with designers and architects to understand specifications at unit/top level Understand use cases and develop functional test plans Develop directed tests written in C, Assembly, and SystemVeri
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Apprenticeship CAI at MediaTek Bangalore

Hello Dear Readers, 

Currently at MediaTek Bangalore vacancy for an Apprenticeship CAI role.

Job Description:
  • B.Tech degree in Electrical/Electronics Engineering with a strong educational background in Digital circuit design
  • Experience in physical design of high performance design with frequencies > 2 Ghz.
  • Experienced in hierarchical design, budgeting, multiple voltage domains and multiple clock domains.
  • Strong skills with Cadence Encounter.
  • Solid understanding of STA and timing constraints.
  • Experienced in working on advanced process nodes (16nm).
  • Strong expertise in Physical Verification to debug LVS/DRC issues at the block level.

Requirement:
  • B.Tech degree in Electrical/Electronics Engineering with strong educational background in Digital circuit design
  • Experience in physical design of high performance design with frequencies > 2 Ghz.
  • Experienced in hierarchical design, budgeting, multiple voltage domains and multiple clock domains.
  • Strong skills with Cadence Encounter.
  • Solid understanding of STA and timing constraints.
  • Experienced in working on advanced process nodes (16nm).
  • Strong expertise in Physical Verification to debug LVS/DRC issues at block level.  

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