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YAML in Semiconductor EDA: From Configuration Language to Reusable Design-Flow Methodology

Hello Dear Readers,   Today in this post, I will provide some deep insight about yaml langauge for CAD flow developments with detailed examples. YAML is not a programming language in the same sense as Python, Tcl, C++, or Verilog. It is primarily a human-readable data serialization/configuration language . In semiconductor EDA, that distinction is important because YAML generally describes what a flow should do , while Python/Tcl/Shell and the EDA tools execute the flow . The official YAML specification describes it as a data serialization language designed to be human-friendly and portable across programming languages. For the semiconductor angle, this becomes particularly interesting because YAML can act as a configuration layer between design methodology and EDA implementation . Frameworks such as Hammer explicitly use YAML/JSON configuration and an intermediate representation to standardize information exchanged between design, technology, and tool plugins. 1. Introduction M...
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RTL Design Engineer at ARM India

 Hello Dear Readers, 

Currently, ARM India has a vacancy for an RTL Design Engineer role.

Arm designs the technology at the heart of sophisticated digital products, from wireless, networking, and consumer entertainment solutions to imaging, automotive, security, and storage devices. Arm improves people’s lives by enabling the intelligence in affordable, easy-to-use electronic products that transform the way we live and work. We work in partnership with a global network of leading technology companies using our experienced low-power technology. Together we are crafting the future of a better world. 

Today, We are well recognized as the market leader in the CPU and System IP industry to name a few and this has been achieved by consistently delivering reliable and high-quality IP products. The cost of design and manufacturing warrants the “right first-time” approach for all IP and System products by our partners. Time-to-market is essential for our partners to look after steadfast competition in the marketplace, being first would enable them to get premium value from the end products. 

Responsibilities: 

As a Design Engineer, you will be a key contributor/leader in a versatile RTL design team. You will own microarchitecture, RTL design, methodologies, process, planning etc. for CPU coherency IP of high performance, energy efficient microprocessors. 

  • Micro-architecture specification development and design
  • Verilog and SystemVerilog RTL development and debug
  • Writing Assertions for RTL code and proving it in Formal verification environment 
  • Working closely with validation, and implementation teams to meet all functional requirements, performance, power and area goals 
  • Planning, tracking, partner communication 
  • Line managing, coaching, mentoring and managing engineers/team 
  • Refining methodologies/process to improve efficiency/quality
  • Exposure to formal verification is helpful 



Required Skills and Experience : 
  • 3+ Years of relevant work experience in developing/leading sophisticated designs preferably of/around CPU/coherency/cache/interconnect/MMU/TLB 
  • Hands-on experience using Verilog HDL for design 
  • Proven experience designing for targeted PPA. Sound ability to make right trade-offs around features, PPA, development cost, verification efficiency/quality etc. 
  • Ability to generate consistent, complete, and concise specifications 
  • Excellent communication (written, verbal, presentations) skills 
  • Co-operate and communicate well with other members of Arm both locally and across sites 
  • Show initiative in identifying solutions to problems of interest to Arm 
  • Be motivated to continuously develop skills and accept a variety of responsibilities. 
  • Some travel outside India to Arm may be required.
  • Strong understanding of CPU Architecture/micro-architectures.


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