Skip to main content

Product Engineer II at Cadence Design Systems

Hello Dear Readers, Cadence Design Systems has a vacancy for a Product Engineer II role. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.  Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage: The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recog...

RTL Design Engineer at ARM India

 Hello Dear Readers, 

Currently, ARM India has a vacancy for an RTL Design Engineer role.

Arm designs the technology at the heart of sophisticated digital products, from wireless, networking, and consumer entertainment solutions to imaging, automotive, security, and storage devices. Arm improves people’s lives by enabling the intelligence in affordable, easy-to-use electronic products that transform the way we live and work. We work in partnership with a global network of leading technology companies using our experienced low-power technology. Together we are crafting the future of a better world. 

Today, We are well recognized as the market leader in the CPU and System IP industry to name a few and this has been achieved by consistently delivering reliable and high-quality IP products. The cost of design and manufacturing warrants the “right first-time” approach for all IP and System products by our partners. Time-to-market is essential for our partners to look after steadfast competition in the marketplace, being first would enable them to get premium value from the end products. 

Responsibilities: 

As a Design Engineer, you will be a key contributor/leader in a versatile RTL design team. You will own microarchitecture, RTL design, methodologies, process, planning etc. for CPU coherency IP of high performance, energy efficient microprocessors. 

  • Micro-architecture specification development and design
  • Verilog and SystemVerilog RTL development and debug
  • Writing Assertions for RTL code and proving it in Formal verification environment 
  • Working closely with validation, and implementation teams to meet all functional requirements, performance, power and area goals 
  • Planning, tracking, partner communication 
  • Line managing, coaching, mentoring and managing engineers/team 
  • Refining methodologies/process to improve efficiency/quality
  • Exposure to formal verification is helpful 



Required Skills and Experience : 
  • 3+ Years of relevant work experience in developing/leading sophisticated designs preferably of/around CPU/coherency/cache/interconnect/MMU/TLB 
  • Hands-on experience using Verilog HDL for design 
  • Proven experience designing for targeted PPA. Sound ability to make right trade-offs around features, PPA, development cost, verification efficiency/quality etc. 
  • Ability to generate consistent, complete, and concise specifications 
  • Excellent communication (written, verbal, presentations) skills 
  • Co-operate and communicate well with other members of Arm both locally and across sites 
  • Show initiative in identifying solutions to problems of interest to Arm 
  • Be motivated to continuously develop skills and accept a variety of responsibilities. 
  • Some travel outside India to Arm may be required.
  • Strong understanding of CPU Architecture/micro-architectures.


Comments

Popular posts from this blog

SDC (Synopsys Design Constraints) contents part 4

Today, we will be discussing the remaining constraints mentioned in the SDC, which pertain to timing exceptions and design rules. This is the final part of the SDC contents. This is going to be interesting, especially with multicycle paths. Take time to read and try to comprehend. 10. set_max_transition     By setting max transition value, our design checks that all ports and pins are meeting the specified limits mentioned in SDC. If these are not satisfied then timing report will give DRVs (design rule violations) in terms of slack. This is specified as               set_max_transition 0.5  UBUF1/A setting maximum limit of 500ps on pin A of Buffer1. 11. set_max_capacitance     This is same as max transition, setting the maximum capacitance value. if our design not meeting this value then violation will occur. This will also reports under design rule violations in terms of slack.     set_max_capacitance 0.7 [all_...

Apprenticeship CAI at MediaTek Bangalore

Hello Dear Readers,   Currently at MediaTek Bangalore vacancy for an Apprenticeship CAI role. Job Description: B.Tech degree in Electrical/Electronics Engineering with a strong educational background in Digital circuit design Experience in physical design of high performance design with frequencies > 2 Ghz. Experienced in hierarchical design, budgeting, multiple voltage domains and multiple clock domains. Strong skills with Cadence Encounter. Solid understanding of STA and timing constraints. Experienced in working on advanced process nodes (16nm). Strong expertise in Physical Verification to debug LVS/DRC issues at the block level. Requirement: B.Tech degree in Electrical/Electronics Engineering with strong educational background in Digital circuit design Experience in physical design of high performance design with frequencies > 2 Ghz. Experienced in hierarchical design, budgeting, multiple voltage domains and multiple clock domains. Strong skills with Cadence Enc...

IC Physical Design (PnR) at Ulkasemi

Hello Dear Readers,   Ulkasemi  has a vacancy for an IC Physical Design (PnR) role. Job Overview: As a full-time Trainee Engineer, the individual will be working on IC Physical Design implementation from RTL to GDSII to create design databases ready for manufacturing with a special focus on power, performance & area optimization with next-generation state-of-the-art process technologies. Job Responsibilities: Perform physical design implementation which includes Floor planning, Power Planning, Clock Tree Synthesis, Place and Route, ECO, Logic Equivalence checks Timing analysis, physical & electrical verification, driving the sign-off closure meeting schedule, and design goals Develop flow, methodologies, and automation scripts for various implementation steps Follow the instructions, compile documents, prepare deliverables, and report to the team lead Should remain up to date with the latest technology trends Educational Qualification:   B.Sc/M.Sc   in EEE or...