Skip to main content

Product Engineer II at Cadence Design Systems

Hello Dear Readers, Cadence Design Systems has a vacancy for a Product Engineer II role. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.  Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage: The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recog...

FPGA Engineer at Lenovo Inc

Hello Dear Readers,

Currently, at Lenovo Inc. vacancy for an FPGA Engineer role.

Lenovo is a US$62 billion revenue global technology powerhouse, ranked #171 in the Fortune Global 500, employing 77,000 people around the world, and serving millions of customers every day in 180 markets. Focused on a bold vision to deliver smarter technology for all, Lenovo has built on its success as the world’s largest PC company by further expanding into growth areas that fuel the advancement of ‘New IT’ technologies (client, edge, cloud, network, and intelligence) including server, storage, mobile, software, solutions, and services.

The role is an FPGA Engineer position in the Lenovo Datacenter Product Group (DCG), based out of Bangalore, Karnataka. This is an exciting role in the Server Development organization that has a strong focus on being the #1 trusted IT Partner in the data center. Opportunities on the team include developing innovative and complex server designs to meet customer and business needs.  These organic designs provide exposure to the latest technologies from Lenovo and its development partners to meet market demands.  The role also offers solving unique client challenges through the custom development of solutions and direct engagement with customers.  This candidate will become an active member of the development team that is highly motivated to engage, understand and solve the technical challenges of today and shape the server designs of tomorrow.


Required skills:

  1.  Bachelor's Degree in Electronics /Computer Engineering.
  2. 2+ years of experience in x86 architecture and hardware design.  Server design experience is preferred.
  3. 2+ year of experience in EDA schematic design tools for PCB schematic creation and the support of Physical design activity
  4. Experience in VHDL or Verilog programming and setting up test benches for verification of FPGA logic.
  5. Responsibilities or server system FPGA/CPLD development, verification, and maintenance 
  6. Maintain relevant design documents.
  7. Work closely with the worldwide hardware and firmware team for issue analysis.  
  8. Experience in simulation of FPGA logic  ModelSIM being the preferred tool currently in use.  
  9. Ability to triage and resolve medium to complex issues as well as experience in defining and performing low-level hardware validation.
  10. Strong teamwork experience to co-develop server subsystems with a team of highly motivated engineers.
  11. Strong written and verbal communication skills for a variety of tasks, including customer engagements, defect investigation, and executive updates.

Preferred skills:

  1. 4+ years of experience in x86 architecture and hardware design.  Server design experience is preferred.
  2. Experience in embedded controllers (ex. PSOC, microcontroller), including schematic design and programming logic.
  3. Proficiency in Linux/Windows Operating systems. Experience with OS virtualization is a plus.
  4. Strong proficiency in shell scripting (BASH/Perl/Python and Windows Power Shell) preferred.
  5. Collaborate on projects across fast-paced global teams.
  6. Provide executive updates in both written and presentation formats.

   

Apply Here

Comments

Popular posts from this blog

SDC (Synopsys Design Constraints) contents part 4

Today, we will be discussing the remaining constraints mentioned in the SDC, which pertain to timing exceptions and design rules. This is the final part of the SDC contents. This is going to be interesting, especially with multicycle paths. Take time to read and try to comprehend. 10. set_max_transition     By setting max transition value, our design checks that all ports and pins are meeting the specified limits mentioned in SDC. If these are not satisfied then timing report will give DRVs (design rule violations) in terms of slack. This is specified as               set_max_transition 0.5  UBUF1/A setting maximum limit of 500ps on pin A of Buffer1. 11. set_max_capacitance     This is same as max transition, setting the maximum capacitance value. if our design not meeting this value then violation will occur. This will also reports under design rule violations in terms of slack.     set_max_capacitance 0.7 [all_...

Apprenticeship CAI at MediaTek Bangalore

Hello Dear Readers,   Currently at MediaTek Bangalore vacancy for an Apprenticeship CAI role. Job Description: B.Tech degree in Electrical/Electronics Engineering with a strong educational background in Digital circuit design Experience in physical design of high performance design with frequencies > 2 Ghz. Experienced in hierarchical design, budgeting, multiple voltage domains and multiple clock domains. Strong skills with Cadence Encounter. Solid understanding of STA and timing constraints. Experienced in working on advanced process nodes (16nm). Strong expertise in Physical Verification to debug LVS/DRC issues at the block level. Requirement: B.Tech degree in Electrical/Electronics Engineering with strong educational background in Digital circuit design Experience in physical design of high performance design with frequencies > 2 Ghz. Experienced in hierarchical design, budgeting, multiple voltage domains and multiple clock domains. Strong skills with Cadence Enc...

IC Physical Design (PnR) at Ulkasemi

Hello Dear Readers,   Ulkasemi  has a vacancy for an IC Physical Design (PnR) role. Job Overview: As a full-time Trainee Engineer, the individual will be working on IC Physical Design implementation from RTL to GDSII to create design databases ready for manufacturing with a special focus on power, performance & area optimization with next-generation state-of-the-art process technologies. Job Responsibilities: Perform physical design implementation which includes Floor planning, Power Planning, Clock Tree Synthesis, Place and Route, ECO, Logic Equivalence checks Timing analysis, physical & electrical verification, driving the sign-off closure meeting schedule, and design goals Develop flow, methodologies, and automation scripts for various implementation steps Follow the instructions, compile documents, prepare deliverables, and report to the team lead Should remain up to date with the latest technology trends Educational Qualification:   B.Sc/M.Sc   in EEE or...