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VLSI Packaging Evolution and Innovations

Hello Dear Readers,   Today in this post, I will provide some deep insight into the VLSI packaging evolution and innovations. Semiconductor packaging has evolved from a simple protective housing into a critical performance enabler. In the modern VLSI landscape, packaging is no longer an afterthought; it is a fundamental determinant of PPA (Power, Performance, and Area) metrics, often dictating the thermal limits and signal integrity of the final SoC. 1. Traditional Packaging Technologies: These methods are the workhorses of the industry, widely used for low-to-medium complexity devices where cost-efficiency is paramount. Wire Bonding (QFN, QFP, DIP): Wire bonding is the most mature interconnection technology. It uses thin gold, copper, or aluminum wires to connect the die's bond pads to the package's internal leadframe. Implementation: The die is attached face-up to a leadframe or substrate. A wire bonder uses thermocompression or ultrasonic energy to attach wires betwee...

FPGA Design Engineer at Bellatrix Aerospace

Hello Dear Readers,

Currently, at Bellatrix Aerospace vacancy for an FPGA Engineer role.

Bellatrix Aerospace is an In-Space Mobility company developing new-age technologies that shape the future of our industry. We specialize in the development and production of propulsion systems and in-orbit transportation solutions. Our work has won two National Awards and backing of the government and many marque investors.


At Bellatrix, we strive to create an environment that rewards creativity, performance and perseverance. At the same time, we also understand that failures are steppingstones to success on a journey to create something that never existing. In other words, our culture is fueled by intellectual curiosity, and our team takes pride in creating technologies that impact India and the world, growing together and achieving their goals each day. 


Job Description:

End-to-end realization of spacecraft embedded systems based on FPGAs including following activities:

1. Design and Development: Develop FPGA designs for all major vendors and device families including Xilinx, Altera, Lattice, and Microsemi (Microchip). Designs are implemented using VHDL and support the full product lifecycle.

2. Verification: Create self-checking and reusable testbenches from scratch. Utilize modern verification methodologies including UVM and assertion-based techniques.

3. Integration: Integrate custom VHDL and Verilog code with third-party IP. Debug and resolve hardware bugs and interoperability issues.

4. Testing and Validation: Perform RTL design and simulation. Conduct timing analysis and closure at the system level.

5. Documentation: Document all aspects of the design process. Create design specifications and theory of operation documentation.

6. Other Responsibilities:

  • Identification of realization plan including prototyping, fabrication, and testing activities.
  • Interactions and technical co-ordination with systems, mechanical, power electronics, embedded electronics, and software team members.
  • Interactions with vendors and coordination with purchase team to procure the required components within stipulated schedule.
  • Conducting functional (both mechanical and electrical-electronic aspects), EMI-EMC tests.
  • Participating in environmental qualification tests.

Key Requirements and Skills:

  • Bachelor's/Master's in Electronics and Communications Engineering or any other relevant field.
  • 2+ Years (Bachelor’s)/1+ Years (Master’s) of experience working on FPGA based embedded systems.
  • Proficiency in hardware description languages such as VHDL, Verilog, and System Verilog for design and verification.
  • Familiarity with FPGA design tools like Xilinx Vivado, Altera Quartus, and ModelSim.
  • Strong understanding of digital design principles, including knowledge of state machines, data flow, system timing, and synchronization.
  • Experience with modern verification methodologies like UVM and assertion-based techniques.
  • Capability of performing RTL design, simulation, and system-level timing analysis.
  • Strong debugging skills to resolve complex hardware and software issues.
  • Good understanding of high-speed serial protocols like PCIe, Ethernet, and HDMI, and memory interfaces like DDR3/DDR4.
  • Additional expertise in C/C++ and/or python programming is desired
  • Strong verbal and written communication skills.
  • Ability to work independently and in collaboration with own team and cross-functional teams

Apply Here

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